Method and structure for forming stairs in three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-11950418-B2
Application number	US-202117218117-A
Country	US
Kind code	B2
Filing date	Mar 30, 2021
Priority date	Nov 5, 2019
Publication date	Apr 2, 2024
Grant date	Apr 2, 2024

Abstract

Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device includes the following operations. A dielectric stack is formed to have interleaved sacrificial layers and dielectric layers. A stair is formed in the dielectric stack. The stair includes one or more sacrificial layers of the sacrificial layers and one or more dielectric layers of the dielectric layers. The stair exposes one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface. An insulating portion is formed to cover the side surface of the stair to cover the one or more sacrificial layers. A sacrificial portion is formed to cover the top surface of the stair. The sacrificial portion is in contact with the one of sacrificial layers. The one or more sacrificial layers and the sacrificial portion are replaced with one or more conductor layers.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising interleaved a plurality of sacrificial layers and a plurality of dielectric layers;
forming a plurality of stairs in the dielectric stack, each stair comprising one or more sacrificial layers of the plurality of sacrificial layers and one or more dielectric layers of the plurality of dielectric layers, each stair exposing one of the sacrificial layers on a top surface and the one or more sacrificial layers on a side surface;
forming an insulating portion to cover the side surface of each stair to cover the one or more sacrificial layers;
forming a sacrificial film, wherein the sacrificial film comprises a first portion covering a side surface of the insulating portion, and a second portion covering the top surface of each stair and a top surface of the insulating portion and being in contact with the one of sacrificial layers;
removing the first portion of the sacrificial film to expose the insulating portion on the side surface of each stair, wherein the second portion is retained covering the top surface of the insulating portion, and a bottom surface of the insulating portion is in contact with a top surface of adjacent lower stair; and
replacing the one or more sacrificial layers and the second portion of the sacrificial film with one or more conductor layers.

2. The method of claim 1 , wherein forming the insulating portion comprises:
forming each stair to expose one of the dielectric layers on the top surface;
forming an insulating layer to cover the top and side surfaces of each stair; and
removing a portion of the insulating layer on the top surface of each stair and the one of the dielectric layers to expose the one of sacrificial layers, a remaining portion of the insulating layer on the side surface of the stair forming the insulating portion.

3. The method of claim 2 , wherein forming the insulating layer comprises performing an atomic layer deposition (ALD).

4. The method of claim 2 , wherein removing the portion of the insulating layer comprises performing an anisotropic etching process.

5. The method of claim 3 , wherein forming the insulating layer comprises depositing a layer of at least one of silicon oxide or high dielectric constant (high-k) dielectric.

6. The method of claim 2 , wherein forming the insulating layer comprises depositing a layer of dielectric material that is different from a material of the sacrificial film.

7. The method of claim 1 , wherein removing the first portion of the sacrificial film comprises performing an isotropic etching process.

8. The method of claim 7 , wherein forming the sacrificial film comprises depositing a film of sacrificial material that is the same as a material of the plurality of sacrificial layers.

9. The method of claim 1 , wherein replacing the one or more sacrificial layers and the second portion of the sacrificial film with one or more conductor layers comprises:
removing the one or more sacrificial layers and the second portion of the sacrificial film to form one or more lateral recesses; and
depositing a conductor material to fill in the lateral recesses and form the one or more conductor layers.

10. The method of claim 9 , further comprising:
forming an insulating structure surrounding the dielectric stack such that the dielectric stack is in the insulating structure; and
forming a contact extending in the insulating structure and in contact with a conductor layer on the top surface of the stair.

11. A method for forming a three-dimensional (3D) memory device, comprising:
forming a plurality of stairs in a dielectric stack comprising interleaved a plurality of sacrificial layers and a plurality of dielectric layers, wherein each stair comprises one or more sacrificial layers of the plurality of sacrificial layers and one or more dielectric layers of the plurality of dielectric layers, each stair exposing one of the dielectric layers on a top surface and the one or more sacrificial layers on a side surface;
forming an insulating portion to cover the side surface of each stair to cover the one or more sacrificial layers;
forming a sacrificial film, wherein the sacrificial film comprises a first portion covering a side surface of the insulating portion, and a second portion covering the top surface of each stair and a top surface of the insulating portion and being in contact with the one of sacrificial layers; and
removing the first portion of the sacrificial film to expose the insulating portion on the side surface of each stair, wherein the second portion is retained covering the top surface of the insulating portion, and a bottom surface of the insulating portion is in contact with a top surface of adjacent lower stair.

12. The method of claim 11 , wherein forming the insulating portion comprises:
forming an insulating layer to cover the top and side surfaces of each stair; and
removing a portion of the insulating layer on the top surface of each stair and the one of the dielectric layers to expose the one of sacrificial layers, a remaining portion of the insulating layer on the side surface of the stair forming the insulating portion.

13. The method of claim 12 , wherein forming the insulating layer comprises performing an atomic layer deposition (ALD).

14. The method of claim 12 , wherein removing the portion of the insulating layer comprises performing an anisotropic etching process.

15. The method of claim 13 , wherein forming the insulating layer comprises depositing a layer of at least one of silicon oxide or high dielectric constant (high-k) dielectric.

16. The method of claim 12 , wherein forming the insulating layer comprises depositing a layer of dielectric material that is different from a material of the sacrificial film.

17. The method of claim 11 , wherein removing the first portion of the sacrificial film comprises performing an isotropic etching process.

18. The method of claim 11 , wherein forming the sacrificial film comprises depositing a film of sacrificial material that is the same as a material of the plurality of sacrificial layers.

19. The method of claim 11 , further comprising: replacing the one or more sacrificial layers and the second portion of the sacrificial film with one or more conductor layers.

20. The method of claim 19 , wherein replacing the one or more sacrificial layers and the second portion of the sacrificial film with one or more conductor layers comprises:
removing the one or more sacrificial layers and the second portion of the sacrificial film to form one or more lateral recesses; and
depositing a conductor material to fill in the lateral recesses and form the one or more conductor layers.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Liu Xinxin
• Geng Jingjing
• Yang Zhu
• Zuo Chen
• Wang Xiangning

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/50 Primary

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title