Vertical memory devices

Patent metadata

Field	Value
Publication number	US-12048153-B2
Application number	US-202117213448-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Jan 15, 2021
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

Aspects of the disclosure provide semiconductor devices. For example, a semiconductor device includes a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate. Then, the semiconductor device includes a memory stack that includes a first stack of alternating gate layers and insulating layers and a second stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate. Further, the semiconductor device includes a joint insulating layer in the second region and a third stack of alternating gate layers and insulating layers in the first region between the first stack of alternating gate layers and insulating layers and the second stack of alternating gate layers and insulating layers.

First claim

What is claimed is:

1. A method for semiconductor device fabrication, comprising:
forming a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate;
forming, in the first region and the second region, a first stack of alternating gate layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate;
forming, in the first region and the second region, a third stack of alternating gate layers and insulating layers;
removing the third stack of alternating gate layers and insulating lavers from the second region to expose the first stack of alternating gate layers and insulating lavers in the second region;
depositing an insulating material on top of the third stack of alternating gate layers and insulating layers remaining in the first region and on top of the first stack of alternating gate layers and insulating layers in the second region;
forming a joint structure in the insulating material in the second region;
depositing a protecting layer on top of the insulating material in the first region and the second region,
polishing to remove the protecting layer and the insulating material in the first region with a stop on the protecting layer in the second region; and
forming a second stack of alternating gate layers and insulating layers on top of the third stack of alternating gate layers and insulating layers in the first region and on top of the insulating material in the second region.

2. The method of claim 1 , wherein the insulating material includes silicon dioxide, and the protecting layer includes silicon nitride.

3. The method of claim 1 , wherein the forming, in the first region and the second region, the third stack of alternating gate layers and insulating layers comprises:
depositing a last sacrificial layer of the sacrificial layers with a larger thickness than other sacrificial layers in the third stack of alternating gate layers and insulating layers.

4. The method of claim 1 , further comprising:
forming, in the second region, a first portion of a channel structure in the first stack of alternating gate layers and insulating layers; and
forming, in the second region, a second portion of the channel structure in the second stack of alternating gate layers and insulating layers,
the joint structure connecting the first portion of the channel structure with the second portion of the channel structure.

5. A method for semiconductor device fabrication, comprising:
forming a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate;
depositing, in the first region and the second region, a first stack of alternating sacrificial layers and insulating layers along a second direction that is perpendicular to the main surface of the substrate;
depositing, in the first region and the second region, a joint insulating layer;
removing the joint insulating layer from the first region; and
depositing, in the first region and the second region, a second stack of alternating sacrificial layers and insulating lavers, wherein
a lowermost sacrificial layer in the second stack of alternating sacrificial layers and insulating layers is deposited on the top of the joint insulating structure in the second region and the first stack of alternating gate layers and insulating layers in the first region.

6. The method of claim 5 , further comprising:
forming, in the second region, a first portion of a channel structure in the first stack of alternating gate layers and insulating layers;
forming, in the second region, a second portion of the channel structure in the second stack of alternating gate layers and insulating layers; and
forming, in the second region, a joint structure in the joint insulating layer, the joint structure connecting the first portion of the channel structure with the second portion of the channel structure.

7. A method for semiconductor device fabrication, comprising:
forming a substrate having a first region and a second region along a first direction that is parallel to a main surface of the substrate;
forming, in the first region and the second region, a first stack of alternating gate layers and insulating along a second direction that is perpendicular to the main surface of the substrate;
forming, in the first region and the second region, a third stack of alternating gate layers and insulating layers;
removing the third stack of alternating gate layers and insulating layers from the second region to expose the first stack of alternating gate layers and insulating layers in the second region;
depositing an insulating material on top of the third stack of alternating gate layers and insulating layers remaining in the first region and on top of the first stack of alternating gate layers and insulating layers in the second region;
forming a joint structure in the insulating material in the second region;
forming an etch protecting mask on top of the insulating material in the second region with the insulating material in the first region being exposed;
etching the insulating material in the first region to expose the third stack of alternating gate layers and insulating layers remaining in the first region based on the etch protecting mask; and
forming a second stack of alternating gate layers and insulating layers on top of the third stack of alternating gate layers and insulating layers in the first region and on top of the insulating material in the second region.

8. The method of claim 7 , wherein the insulating material includes silicon dioxide, and the etch protecting mask includes silicon nitride.

9. The method of claim 7 , wherein the forming, in the first region and the second region, the third stack of alternating gate layers and insulating layers comprises:
depositing a last sacrificial layer of the sacrificial layers with a larger thickness than other sacrificial layers in the third stack of alternating gate layers and insulating layers.

10. The method of claim 7 , further comprising:
forming, in the second region, a first portion of a channel structure in the first stack of alternating gate layers and insulating layers; and
forming, in the second region, a second portion of the channel structure in the second stack of alternating gate layers and insulating layers, the joint structure connecting the first portion of the channel structure with the second portion of the channel structure.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Qiangwei
• Geng Jingjing
• Yuan Bin
• Wang Xiangning
• Zuo Chen
• Yang Zhu
• Cheng Liming
• Guo Zhen

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title