Three-dimensional memory devices having isolation structure for source select gate line and methods for forming the same

Patent metadata

Field	Value
Publication number	US-2022077181-A1
Application number	US-202017084378-A
Country	US
Kind code	A1
Filing date	Oct 29, 2020
Priority date	Sep 4, 2020
Publication date	Mar 10, 2022
Grant date	—

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack on the substrate, a plurality of channel structures each extending vertically through the memory stack, an isolation structure, and an alignment mark. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. An outmost one of the conductive layers toward the substrate is a source select gate line (SSG). The isolation structure extends vertically into the substrate and surrounds at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure. The alignment mark extends vertically into the substrate and is coplanar with the isolation structure.

First claim

What is claimed is:

1 . A three-dimensional (3D) memory device, comprising:
a substrate; a memory stack on the substrate comprising a plurality of interleaved conductive layers and dielectric layers, an outermost one of the conductive layers toward the substrate being a source select gate line (SSG); a plurality of channel structures each extending vertically through the memory stack; an isolation structure extending vertically into the substrate and surrounding at least one of the channel structures in a plan view to separate the SSG and the at least one channel structure; and an alignment mark extending vertically into the substrate and coplanar with the isolation structure.

2 . The 3D memory device of claim 1 , wherein the plurality of channel structures are disposed in a core array region and an edge region in a plan view, and the at least one channel structure is disposed in the edge region.

3 . The 3D memory device of claim 2 , wherein the memory stack comprises a staircase structure, the edge region is laterally between the staircase structure and the core array region, and the at least one channel structure is disposed in an outmost column adjacent to the staircase structure in the plan view.

4 . The 3D memory device of claim 2 , wherein a lateral dimension of the at least one channel structure is greater than a lateral dimension of the channel structures disposed in the core array region.

5 . The 3D memory device of claim 1 , wherein a lateral distance between the SSG and the at least one channel structure is between about 40 nm and about 80 nm.

6 . The 3D memory device of claim 1 , wherein each of the channel structures comprises a semiconductor plug at one end toward the substrate.

7 . The 3D memory device of claim 6 , wherein the isolation structure is laterally between the SSG and the semiconductor plug of the at least one channel structure.

8 . The 3D memory device of claim 6 , wherein the semiconductor plug of the at least one channel structure extends into the substrate further than a semiconductor plug of another one of the channel structures.

9 . The 3D memory device of claim 1 , wherein the isolation structure and the alignment mark each comprise a dielectric.

10 . The 3D memory device of claim 1 , wherein the alignment mark extends vertically through the SSG.

11 . The 3D memory device of claim 1 , further comprising an SSG cut extending vertically into the substrate and coplanar with the isolation structure and the alignment mark.

12 . A three-dimensional (3D) memory device, comprising:
a substrate; a source select gate line (SSG) extending laterally; an isolation structure extending vertically through the SSG into the substrate; a first channel structure extending vertically through the SSG into the substrate; and a second channel structure extending vertically through the isolation structure into the substrate and spaced apart from the SSG by the isolation structure.

13 . The 3D memory device of claim 12 , wherein the first channel structure is disposed in a core array region, and the second channel structure is disposed in an edge region in a plan view.

14 . The 3D memory device of claim 12 , wherein the second channel structure extends into the substrate further than the first channel structures.

15 . The 3D memory device of claim 12 , further comprising:
an alignment mark extending vertically through the SSG into the substrate and coplanar with the isolation structure; and an SSG cut extending vertically through the SSG into the substrate and coplanar with the isolation structure and the alignment mark.

16 . A method for forming a three-dimensional (3D) memory device, comprising:
forming a source select gate line (SSG) sacrificial layer above a substrate; simultaneously forming an isolation structure and an alignment mark each through the SSG sacrificial layer into the substrate; forming a plurality of interleaved word line dielectric layers and word line sacrificial layers above the SSG sacrificial layer, the isolation structure, and the alignment mark; forming a first channel structure extending vertically through the interleaved word line dielectric layers and word line sacrificial layers and the isolation structure; and replacing the word line sacrificial layers and the SSG sacrificial layer with a plurality of conductive layers to form a plurality of word lines and an SSG, respectively, such that the first channel structure is spaced apart from the SSG by the isolation structure.

17 . The method of claim 16 , further comprising forming a second channel structure extending vertically through the interleaved word line dielectric layers and word line sacrificial layers and the SSG sacrificial layer in a same process for forming the first channel structure, wherein the second channel structure is in contact with the SSG by replacing the word line sacrificial layers and the SSG sacrificial layer with the plurality of conductive layers to form the plurality of word lines and the SSG.

18 . The method of claim 17 , wherein simultaneously forming the isolation structure and the alignment mark comprises:
simultaneously etching an isolation trench and an alignment trench each through the stop layer, the buffer layer, and the SSG sacrificial layer into the substrate; depositing a dielectric layer to fill the isolation trench and the alignment trench; planarizing the dielectric layer stopping at the stop layer; and removing the stop layer.

19 . The method of claim 18 , further comprising, after removing the stop layer, planarizing the dielectric layer and the buffer layer to form the isolation structure and the alignment mark.

20 . The method of claim 16 , further comprising forming an SSG cut through the SSG sacrificial layer in a same process of forming the isolation structure and the alignment mark.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Guo Zhen
• Geng Jingjing
• Yuan Bin
• Wu Jiajia
• Wang Xiangning
• Yang Zhu
• Zuo Chen

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L2223/54426

  Electricity · mapped topic