Advanced transistors with punch through suppression
US-10325986-B2 · Jun 18, 2019 · US
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Thompson Scott E patents
Thompson Scott E is listed as an inventor on 52 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Thompson Scott E |
| Total patents | 52 |
| First publication | May 26, 2015 |
| Latest publication | Jun 18, 2019 |
Notable patents
Publications ranked by popularity score, then publication date.
Digital circuits having improved transistors, and methods therefor
US-10250257-B2 · Apr 2, 2019 · US
Electronic devices and systems, and methods for making and using the same
US-2019080967-A1 · Mar 14, 2019 · US
Electronic devices and systems, and methods for making and using the same
US-10224244-B2 · Mar 5, 2019 · US
Electronic devices and systems, and methods for making and using the same
US-10217668-B2 · Feb 26, 2019 · US
Electronic devices and systems, and methods for making and using same
US-10074568-B2 · Sep 11, 2018 · US
Digital Circuits Having Improved Transistors, and Methods Therefor
US-2018248548-A1 · Aug 30, 2018 · US
Buried channel deeply depleted channel transistor
US-9991300-B2 · Jun 5, 2018 · US
Digital circuits having improved transistors, and methods therefor
US-9985631-B2 · May 29, 2018 · US
Integrated circuit devices and methods
US-9966130-B2 · May 8, 2018 · US
Recent patents
Latest publications not already listed above.
Transistor with threshold voltage set notch and method of fabrication thereof
US-9922977-B2 · Mar 20, 2018 · US
Digital Circuits Having Improved Transistors, and Methods Therefor
US-2018048311-A1 · Feb 15, 2018 · US
Low power semiconductor transistor structure and method of fabrication thereof
US-9865596-B2 · Jan 9, 2018 · US
Digital circuits having improved transistors, and methods therefor
US-9838012-B2 · Dec 5, 2017 · US
Buried Channel Deeply Depleted Channel Transistor
US-2017323916-A1 · Nov 9, 2017 · US
Integrated Circuit Devices and Methods
US-2017301395-A1 · Oct 19, 2017 · US
Buried channel deeply depleted channel transistor
US-9786703-B2 · Oct 10, 2017 · US
Integrated circuit devices and methods
US-9741428-B2 · Aug 22, 2017 · US
Digital Circuits Having Improved Transistors, and Methods Therefor
US-2017214404-A1 · Jul 27, 2017 · US
Digital circuits having improved transistors, and methods therefor
US-9680470-B2 · Jun 13, 2017 · US
Electronic Devices and Systems, and Methods for Making and Using the Same
US-2017117366-A1 · Apr 27, 2017 · US
Advanced Transistors with Punch Through Suppression
US-2017040419-A1 · Feb 9, 2017 · US
Buried Channel Deeply Depleted Channel Transistor
US-2017025457-A1 · Jan 26, 2017 · US
Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof
US-2017012044-A1 · Jan 12, 2017 · US
Electronic Devices and Systems, and Methods for Making and Using the Same
US-2016358918-A1 · Dec 8, 2016 · US
Advanced transistors with punch through suppression
US-9508800-B2 · Nov 29, 2016 · US
CMOS gate stack structures and processes
US-9508728-B2 · Nov 29, 2016 · US
Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof
US-2016336318-A1 · Nov 17, 2016 · US
Low power semiconductor transistor structure and method of fabrication thereof
US-9496261-B2 · Nov 15, 2016 · US
Buried channel deeply depleted channel transistor
US-9478571-B1 · Oct 25, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Mie Fujitsu Semiconductor Ltd | 52 |
| Suvolta Inc | 5 |
| Shifren Lucian | 1 |
| Ranade Pushkar | 1 |
| Hoffmann Thomas | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D62/371 | 40 |
| H10D30/601 | 35 |
| H10D84/038 | 30 |
| H10B10/12 | 26 |
| H10D84/83 | 24 |