Digital circuits having improved transistors, and methods therefor

Patent metadata

Field	Value
Publication number	US-9985631-B2
Application number	US-201715795912-A
Country	US
Kind code	B2
Filing date	Oct 27, 2017
Priority date	Feb 18, 2011
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

First claim

What is claimed is:

1. A digital logic circuit, comprising:
a plurality of MOSFET transistors constituting a current steering logic circuit including respective first and second output nodes, a first current source, a second current source, a current sink, and a logic section;
wherein the first and the second current sources are connected in parallel between a logic high node and the logic section, the first current source provides a current to the logic section via a first input current path, the second current source provides a current to the logic section via a second input current path;
wherein the logic section steers current from either of the first and the second input current path to the current sink according to input values of the logic section, and thus generates complementary output signals; and
wherein each of the plurality of transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Thompson Scott E
• Clark Lawrence T

Classifications

• H03K19/0948

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H10D84/836

  comprising EDMOS · CPC title

• H01L27/11807

  Electricity · mapped topic