Integrated circuit devices and methods

Patent metadata

Field	Value
Publication number	US-9741428-B2
Application number	US-201615134640-A
Country	US
Kind code	B2
Filing date	Apr 21, 2016
Priority date	May 13, 2011
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.

First claim

What is claimed is:

1. An integrated circuit comprising:
multiple static random access memory (SRAM) cells, each SRAM cell having at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate;
at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and
a bias voltage network operable to apply one bias voltage to the SRAM cell that is being accessed for a read operation and the other bias voltage to the other SRAM cells that are being not accessed for the read operation.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Clark Lawrence T
• Thompson Scott E
• Roy Richard S
• Rogenmoser Robert
• Thummalapally Damodar R

Classifications

• G11C11/419

  Read-write [R-W] circuits · CPC title

• G11C7/02 Primary

  with means for avoiding parasitic signals · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title