Buried channel deeply depleted channel transistor

Patent metadata

Field	Value
Publication number	US-9786703-B2
Application number	US-201615285308-A
Country	US
Kind code	B2
Filing date	Oct 4, 2016
Priority date	May 24, 2013
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having at least one device region of a first conductivity type;
a source region and a drain region of a second conductivity type formed in the at least one device region and separated by a channel length;
a channel region of the second conductivity type formed in the at least one device region between the source region and the drain region; and
a screening region of the first conductivity type formed in the at least one device region below the channel region and between the source region and the drain region, an effective doping density of the screening region being substantially higher than an effective doping density of the at least one device region; and
a gate structure formed on the at least one device region above the channel region,
wherein the channel region is modified, in response to a bias voltage at the gate structure, to provide a surface depletion layer below the gate structure, a buried depletion layer at an interface of the channel region and the screening region, and a buried channel layer between the surface depletion layer and the buried depletion layer electrically coupling the source region and the drain region, and
wherein the buried depletion layer is substantially located in channel region.

2. The semiconductor of claim 1 wherein the channel region has an effective doping density of the second conductivity type less than an effective doping density of the second conductivity type for the source region and the drain region and less than an effective doping density of the first conductivity type for the screening region.

3. The semiconductor device of claim 1 , wherein the channel region has an effective doping density that is less than 1/10 of an effective doping density of the source region and the drain region.

4. The semiconductor of claim 1 , wherein the screening region has an effective doping density of between about 10 18 cm −3 to 5×10 20 cm −3 .

5. The semiconductor device of claim 1 , wherein the buried depletion layer is completely located in the channel region.

6. The semiconductor device of claim 1 , further comprising:
a gate control circuit, the gate control circuit comprising a reset transistor and a photodiode electrically coupled in series between a first reference voltage node and a second reference voltage node; and
an output circuit electrically coupled to the source region,
wherein the drain region is electrically coupled to a power supply node, and wherein the gate structure is electrically coupled to a portion of the gate control circuit between the reset transistor and the photodiode to define a gate control node.

7. The semiconductor device of claim 6 , wherein the gate control circuit further comprises a transfer gate electrically coupled in series between the gate control node and the photodiode, and wherein the output circuit comprises a pass transistor.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Bakhishev Teymur
• Wang Lingquan
• Zhao Dalong
• Ranade Pushkar
• Thompson Scott E

Classifications

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H01L29/7833

  Electricity · mapped topic

• H01L27/14616 Primary

  Electricity · mapped topic

• H01L29/1087

  Electricity · mapped topic

• H01L29/105

  Electricity · mapped topic