Electronic devices and systems, and methods for making and using the same

Patent metadata

Field	Value
Publication number	US-10224244-B2
Application number	US-201615241337-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Sep 30, 2009
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first CMOS circuit and a second CMOS circuit comprising deeply depleted channel (DDC) field effect transistors (FETs);
each of the DDC FETs having a well with a first conductive type, a screening region with the first conductive type on the well, an un-doped channel layer above the screening region, a threshold voltage tuning region with the first conductive type positioned between the un-doped channel layer and the screening region to modify a threshold voltage of the DDC FETs, a gate stack positioned above the un-doped channel layer to control conduction between a drain and source positioned at both sides of the gate stack;
wherein a dopant concentration of the threshold voltage tuning region is lower than a dopant concentration of the screening region;
wherein there is not a local minimum between the threshold voltage tuning region and the screening region in a depth profile of the first type of dopant;
wherein the screening region sets a depth of a depletion layer below the gate stack in a direction from the un-doped channel layer toward the screening region; and
wherein the well of the first CMOS circuit is applied with a first body bias voltage and the well of the second CMOS circuit is applied with a second body bias voltage different from the first body bias voltage.

2. The semiconductor device of claim 1 , wherein the first mode or the second mode is set statically.

3. The semiconductor device of claim 1 , further comprising:
a punch through suppression region with the first conductive type positioned between the screening region and the well, a dopant concentration of the punch through suppression region are lower than a dopant concentration of the screening region.

4. The semiconductor device of claim 1 , wherein the depletion layer does not go through the screening region, regardless of the first body bias voltage and the second body bias voltage when a voltage of the gate stack equals to the threshold voltage.

5. The semiconductor device of claim 1 , wherein the first mode or the second mode is set dynamically.

6. The semiconductor device of claim 5 , wherein the mode is set statically.

7. The semiconductor device of claim 5 , wherein the mode is set dynamically.

8. A semiconductor device comprising a first circuit block and a second circuit block:
a first circuit block comprising a first field effect transistor:
the first field effect transistor comprising;
a first doped well being doped with a first type of dopant and having a first dopant concentration;
a first gate positioned above the first doped well to control conduction between a first drain and a first source;
a first undoped channel having a second dopant concentration of less than 5× 10 17 atoms/cm 3 , the first undoped channel being situated between the first drain and the first source and below the first gate;
a first screening region being doped with the first type of dopant and having a third dopant concentration greater than ten times the second dopant concentration and greater than the first dopant concentration the first screening region positioned on the first doped well;
a first threshold voltage tuning region positioned between the first undoped channel and the first screening region to modify a threshold voltage of the first field effect transistor, the first threshold voltage tuning region being doped with the first type of dopant and having a fourth dopant concentration less than the third dopant concentration; and
a first body tap electrically coupled to the first doped well such that the first doped well is supplied with a first body bias voltage,

a second circuit block comprising a second field effect transistor:
the second field effect transistor comprising;
a second doped well being doped with a second type of dopant and having a fifth dopant concentration;
a second gate positioned above the second doped well to control conduction between a second drain and a second source;
a second undoped channel having a sixth dopant concentration of less than 5× 10 17 atoms/cm, the second undoped channel being situated between the second drain and the source and below the second gate;
a second screening region being doped with the second type of dopant and having a seventh dopant concentration greater than ten times the sixth dopant concentration and greater than the fifth dopant concentration, the second screening region positioned on the second doped well;
a second threshold voltage tuning region positioned between the second undoped channel and the second screening region to modify a threshold voltage of the second field effect transistor, the threshold voltage tuning region being doped with the second type of dopant and having an eighth dopant concentration less than the seventh dopant concentration,
a second body tap electrically coupled to the second doped well such that the second doped well is supplied with a second body bias voltage,
wherein the first doped well is isolated from the second doped well, the first body bias voltage is supplied independently from the second body bias voltage, and the first circuit block operates at a first mode different from a second mode at which the second circuit block operates;
wherein the first screening region sets a depth of a depletion layer below the first gate stack in a direction from the first un-doped channel layer toward the first screening region; and
wherein there is not a local minimum between the first threshold voltage tuning region and the first screening region in a depth profile of the first type of dopant.

9. The semiconductor device of claim 8 , wherein
the first field effect transistor further comprising a first punch through suppression region positioned between the first screening region and the first doped well, the first punch through suppression region being doped with the first type of dopant and having a fifth dopant concentration :less than the third dopant concentration; and
the second field effect transistor comprising a second punch through suppression region positioned between the second screening region and the second doped well, the second punch through suppression region being doped with the second type of dopant and having a ninth dopant concentration less than the seventh dopant concentration.

10. A semiconductor device comprising a plurality of circuit blocks:
each of the circuit blocks comprising a field effect transistor;
the field effect transistor comprising;
a doped well being doped with a first type of dopant and having a first dopant concentration;
a gate positioned above the doped well to control conduction between a drain and source;
an undoped channel having a second dopant concentration of less than 5 × 10 17 atoms/cm 3 , the undoped channel being situated between the drain and the source and below the gate;
a screening region being doped with the first type of dopant and having a third dopant concentration greater than ten times the second dopant concentration and greater than the first dopant concentration, the screening region positioned on the doped well;

a threshold voltage tuning region positioned between the =doped channel and the screening region to modify a threshold voltage of the field effect transistor, the threshold voltage tuning region being doped with the first type of dopant and having a fourth dopant concentration less than the third dopant concentration;
a body tap electrically coupled to the doped well such that the doped well is supplied with a body bias voltage,
wherein the screening region sets a depth of a depletion layer below the gate stack in a direction from the un-doped channel layer toward the screening

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Thompson Scott E
• Thummalapally Damodar R

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H01L21/84

  Electricity · mapped topic

• H01L29/1083

  Electricity · mapped topic