Electronic Devices and Systems, and Methods for Making and Using the Same

Patent metadata

Field	Value
Publication number	US-2016358918-A1
Application number	US-201615241337-A
Country	US
Kind code	A1
Filing date	Aug 19, 2016
Priority date	Sep 30, 2009
Publication date	Dec 8, 2016
Grant date	—

Abstract

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

First claim

1 - 21 . (canceled)

22 . A semiconductor device, comprising:
a first and a second CMOS circuits formed in respective wells and comprising deeply depleted channel (DDC) field effect transistors (FETs); each of the DDC FETs having a screening region being electrically coupled to each of the respective wells, an un-doped channel layer above the screening region, a gate stack positioned above the un-doped channel region to control conduction between a drain and source positioned at both sides of the gate stack; wherein the well of the first CMOS circuit is applied with a first body bias voltage and the well of the second CMOS circuit is applied with a second body bias voltage different from the first body bias voltage.

23 . A semiconductor device comprising a first circuit block and a second circuit block:
a first circuit block comprising a first field effect transistor: the first field effect transistor comprising;
a first doped well having a first dopant concentration;
a first gate positioned above the first doped well to control conduction between a first drain and source;
a first undoped channel having a second dopant concentration of less than 5×10 17 atoms/cm 3 , the first undoped channel being situated between the first drain and the first source and below the first gate;
a first screening region having a third dopant concentration greater than ten times the second dopant concentration of the first undoped channel and greater than the first dopant concentration;
a first threshold voltage tuning region positioned between the first undoped channel and the first screening region to modify the threshold voltage of the first field effect transistor, the first threshold voltage tuning region having a fourth dopant concentration less than the third dopant concentration; and
a first body tap electrically coupled to the first doped well such that the first doped well is supplied with a first body bias voltage,
a second circuit block comprising a second field effect transistor:
the second field effect transistor comprising;
a second doped well having a fifth dopant concentration;
a second gate positioned above the second doped well to control conduction between a second drain and source;
a second undoped channel having a sixth dopant concentration of less than 5×1017 atoms/cm3, the second undoped channel being situated between the second drain and the source and below the second gate; and
a second screening region having a seventh dopant concentration greater than ten times the sixth dopant concentration of the second undoped channel and greater than the fifth dopant concentration; and
a second threshold voltage tuning region positioned between the second undoped channel and the second screening region to modify the threshold voltage of the second field effect transistor, the threshold voltage tuning region having a eighth dopant concentration less than the seventh dopant concentration,
a second body tap electrically coupled to the second doped well such that the second doped well is supplied with a second body bias voltage,
wherein the first doped well is isolated from the second doped well, the first body bias voltage is supplied independently from the second body bias voltage, and the first circuit block operates at a first mode different from a second mode at which the second circuit block operates.

24 . The semiconductor device of claim 22 , wherein the first mode or the second mode is set statically.

25 . The semiconductor device of claim 22 , wherein the first mode or the second mode is set dynamically.

26 . A semiconductor device comprising a plurality of circuit blocks:
each of the circuit blocks comprising a field effect transistor; the field effect transistor comprising;
a doped well having a first dopant concentration;
a gate positioned above the doped well to control conduction between a drain and source;
a undoped channel having a second dopant concentration of less than 5×10 17 atoms/cm 3 , the undoped channel being situated between the drain and the first source and below the gate;
a screening region having a third dopant concentration greater than ten times the second dopant concentration of the undoped channel and greater than the first dopant concentration;
a threshold voltage tuning region positioned between the undoped channel and the screening region to modify the threshold voltage of the field effect transistor, the threshold voltage tuning region having a fourth dopant concentration less than the third dopant concentration; and
a body tap electrically coupled to the doped well such that the doped well is supplied with a body bias voltage,
wherein each of the circuit blocks has the doped well isolated from other circuit blocks, each of the body bias voltage of the plurality of circuit blocks is independent to each other, and each of the circuit blocks operates at a mode different from each other.

27 . The semiconductor device of claim 25 , wherein the mode is set statically.

28 . The semiconductor device of claim 25 , wherein the mode is set dynamically.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Thompson Scott E
• Thummalapally Damodar R

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title