Transistor with threshold voltage set notch and method of fabrication thereof

Patent metadata

Field	Value
Publication number	US-9922977-B2
Application number	US-201615192288-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 22, 2010
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV T (variation in V T ) compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the V T setting within a precise range. This V T set range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of V T settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control V T (with a low σV T ) and V DD (the operating voltage supplied to the transistor), so that the body bias can be tuned separately from V T for a given device.

First claim

What is claimed is:

1. An integrated circuit die containing a first device of a first conductive type and a second device of a second conductive type different from the first conductive type,
the first device of the first conductive type comprising:
a first well of the first conductive type in a semiconductor substrate;
a first shallow well of the second conductive type on the first well;
a first screening layer on the first shallow well;
a first threshold voltage tuning layer on the first screening layer to provide a first threshold voltage set notch by a doping combination of at least the first screening layer and the first threshold voltage tuning layer;
a first substantially undoped channel layer on the first threshold voltage tuning layer; and
a first gate stack having a first work function on the first substantially undoped channel layer;
the second device of the second type comprising:
a second well of the first conductive type in the semiconductor substrate;
a second screening layer on the second well;
a second threshold voltage tuning layer on the second screening layer to provide a second threshold voltage set notch by a doping combination of at least the second screening layer and the second threshold voltage tuning layer;
a second substantially undoped channel layer on the second threshold voltage tuning layer;
a second gate stack having a second work function on the second substantially undoped channel layer; and
an isolation film formed in the semiconductor substrate separates the first device from the second device,
wherein the first threshold voltage tuning layer comprises such dopants concentration that a first vertical dopant profile formed by the first channel layer, the first threshold voltage tuning layer, and the first screening layer, creates the first threshold set notch with a shallow configuration, and wherein the second threshold voltage tuning layer comprises such dopants concentration that a second vertical dopant profile formed by the second channel layer, the second threshold voltage tuning layer, and the second screening layer, creates the second threshold set notch, and wherein the first shallow well is separated from the semiconductor substrate by the isolation film and the first well.

2. The integrated circuit die of claim 1 , further comprising:
a body tap coupled to the second well, the body tap operable to selectively apply a bias thereto to adjust a threshold voltage of the second device.

3. An integrated circuit die containing a first device of a first conductive type and a second device of a second conductive type different from the first conductive type,
the first device of the first conductive type comprising:
a first well of the first conductive type in a semiconductor substrate;
a first shallow well of the second conductive type on the first well;
a first screening layer on the first shallow well;
a first threshold voltage tuning layer above the first screening layer to provide a first threshold voltage set notch by a doping combination of at least the first screening layer and the first threshold voltage tuning layer;
a first dopant migration resistant layer between the first threshold voltage tuning layer and the first screening layer;
a first substantially undoped channel layer on the first threshold voltage tuning layer; and
a first gate stack having a first work function on the first substantially undoped channel layer;
the second device of the second type comprising:
a second well of the first conductive type in the semiconductor substrate;
a second screening layer on the second well;
a second threshold voltage tuning layer above the second screening layer to provide a second threshold voltage set notch by a doping combination of at least the second screening layer and the second threshold voltage tuning layer;
a second substantially undoped channel layer on the second threshold voltage tuning layer;
a second gate stack having a second work function on the second substantially undoped channel layer; and
an isolation film formed in the semiconductor substrate separates the first device from the second device,
wherein the first threshold voltage tuning layer comprises such dopants concentration that a first vertical dopant profile formed by the first channel layer, the first threshold voltage tuning layer, and the first screening layer, creates the first threshold set notch, and wherein the second threshold voltage tuning layer comprises such dopants concentration that a second vertical dopant profile formed by the second channel layer, the second threshold voltage tuning layer, and the second screening layer, creates the second threshold set notch, and wherein the first shallow well is separated from the semiconductor substrate by the isolation film and the first well.

4. An integrated circuit die containing a first device of a first conductive type and a second device of a second conductive type different from the first conductive type,
the first device of the first conductive type comprising:
a first well of the first conductive type in a semiconductor substrate;
a first shallow well of the second conductive type on the first well;
a first screening layer on the first shallow well;
a first threshold voltage tuning layer on the first screening layer to provide a first threshold voltage set notch by a doping combination of at least the first screening layer and the first threshold voltage tuning layer;
a first substantially undoped channel layer on the first threshold voltage tuning layer; and
a first gate stack having a first work function on the first substantially undoped channel layer;
the second device of the second type comprising:
a second well of the first conductive type in the semiconductor substrate;
a second screening layer on the second well;
a second threshold voltage tuning layer above the second screening layer to provide a second threshold voltage set notch by a doping combination of at least the second screening layer and the second threshold voltage tuning layer;
a second dopant migration resistant layer between the second threshold voltage tuning layer and the second screening layer;
a second substantially undoped channel layer on the second threshold voltage tuning layer;
a second gate stack having a second work function on the second substantially undoped channel layer; and
an isolation film formed in the semiconductor substrate separates the first device from the second device,
wherein the first threshold voltage tuning layer comprises such dopants concentration that a first vertical dopant profile formed by the first channel layer, the first threshold voltage tuning layer, and the first screening layer, creates the first threshold set notch, and wherein the second threshold voltage tuning layer comprises such dopants concentration that a second vertical dopant profile formed by the second channel layer, the second threshold voltage tuning layer, and the second screening layer, creates the second threshold set notch, and wherein the first shallow well is separated from the semiconductor substrate by the isolation film and the first well.

5. The integrated circuit die of claim 1 , wherein the first gate stack comprises metal or nitride of metal.

6. The integrated circuit die of claim 1 , wherein the second gate stack comprises metal or nitride of metal.

7. The integrated circuit die of claim 1 , wherein second threshold set notch has a shallow configuration.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Arghavani Reza
• Ranade Pushkar
• Shifren Lucian
• Thompson Scott E
• De Villeneuve Catherine

Classifications

• H01L29/105

  Electricity · mapped topic

• H01L29/7836

  Electricity · mapped topic

• H01L21/82345

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L21/823842

  Electricity · mapped topic