Digital circuits having improved transistors, and methods therefor

Patent metadata

Field	Value
Publication number	US-9680470-B2
Application number	US-201514867506-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Feb 18, 2011
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

First claim

What is claimed is:

1. A digital logic circuit, comprising:
a plurality of MOSFET transistors coupled by way of a plurality of controllable current paths to at least a first and second logic node to produce a predefined logic function: wherein the plurality of transistors includes at least one precharge transistor that couples a precharge node to the first logic node in response to a first clock signal;
wherein the plurality of transistors includes at least one evaluation transistor that couples a discharge node to the second logic node in response to a second clock signal;
wherein the plurality of transistors are configured to selectively couple an output node to the first or second logic node in response to at least one input signal, the plurality of transistors having gates coupled to receive at least one input signal and source-drain paths coupled to the at least one output node;
wherein each of the plurality of transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region.

2. The circuit of claim 1 , wherein at least some of the plurality of transistors have a strong body coefficient sufficient to receive a bias signal to a transistor body.

3. The circuit of claim 2 , wherein each of the plurality of transistors further includes a heavily doped screen layer below the blanket epitaxial layer.

4. The circuit of claim 3 , wherein the digital logic circuit is configured to provide and receive signals from a static random access memory cell.

5. The circuit of claim 1 , wherein each of the plurality of transistors includes a well having a preselected dopant profile, the dopant profile configured so that a predefined portion of the channel remains substantially undoped, the preselected dopant profile having a notched profile in the continuum of dopant concentration.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Thompson Scott E
• Clark Lawrence T

Classifications

• G11C11/412

  using field-effect transistors only · CPC title

• H03K19/0948

  using CMOS {or complementary insulated gate field-effect transistors} · CPC title

• H03K19/0013 Primary

  in field effect transistor circuits · CPC title

• H10D84/836

  comprising EDMOS · CPC title

• H01L27/1104

  Electricity · mapped topic