Electronic devices and systems, and methods for making and using same

Patent metadata

Field	Value
Publication number	US-10074568-B2
Application number	US-201514642156-A
Country	US
Kind code	B2
Filing date	Mar 9, 2015
Priority date	Sep 30, 2009
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced sigma V T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

First claim

What is claimed is:

1. A method for forming two separate groups of biasable, deeply depleted channel (DDC), field effect transistors (FET) on a die on a wafer, comprising:
implanting at least two screening regions into at least two wells formed on the die on the wafer, the two screening regions being respectively doped with a dopant to have a dopant concentration between 5×10 18 to 1×10 20 atoms/cm 3 , the two screening regions being electrically coupled to respective wells, the two screening regions being positioned to set channel depletion depth during DDC FET operation;
forming at least two undoped semiconductive layers above the two screening regions, with each undoped semiconductive layer having a defined thickness, each undoped semiconductive layer being coextensive with its respective screening region;
forming threshold voltage tuning regions above the two screening regions, with formation of the threshold voltage tuning regions occuring before deposition of the two undoped semiconductive layers forming the undoped channel regions;
maintaining throughout processing at least a portion of the at least two undoped semiconductive layers as undoped channel regions;
forming gate stacks positioned above the undoped channel regions to control conduction between drains and sources;
forming an isolation structure to electrically separate at least two wells and two screening regions supporting transistors formed on the die on the wafer; and
forming at least two body taps respectively electrically coupled to the two wells and the two screening regions.

2. The method of claim 1 , further comprising forming the two undoped semiconductive layers above the two screening regions by depositing an epitaxial silicon layer.

3. The method of claim 1 , further comprising forming the two undoped semiconductive layers above the two screening regions by atomic layer deposition.

4. The method of claim 1 , wherein the at least two undoped semiconductive layers have identical thickness.

5. The method of claim 1 , wherein the at least two undoped semiconductive layers have differing thickness.

6. A method for forming two separate groups of biasable, deeply depleted channel (DDC), field effect transistors (FET) on a die on a wafer, comprising:
implanting at least two screening regions into at least two wells formed on the die on the wafer, the two screening regions being respectively doped with a dopant to have a dopant concentration between 5×10′ 8 to 1×10 20 atoms/cm 3 , the two screening regions being electrically coupled to respective wells, the two screening regions being positioned to set channel depletion depth during DDC FET operation;
forming at least two undoped semiconductive layers above the two screening regions, with each undoped semiconductive layer having a defined thickness, each undoped semiconductive layer being coextensive with its respective screening region;
implanting carbon into the two screening regions below the two undoped semiconductive layers;
maintaining throughout processing at least a portion of the at least two undoped semiconductive layers as undoped channel regions;
forming gate stacks positioned above the undoped channel regions to control conduction between drains and sources;
forming an isolation structure to electrically separate at least two wells and two screening regions supporting transistors formed on the die on the wafer; and
forming at least two body taps respectively electrically coupled to the two wells and the two screening regions.

7. The method of claim 1 , wherein the at least two undoped semiconductive layers have identical thickness.

8. The method of claim 6 , wherein the at least two undoped semiconductive layers have differing thickness.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Thompson Scott E
• Thummalapally Damodar R

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H01L21/823493

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic