Advanced transistors with punch through suppression

Patent metadata

Field	Value
Publication number	US-10325986-B2
Application number	US-201615298913-A
Country	US
Kind code	B2
Filing date	Oct 20, 2016
Priority date	Sep 30, 2009
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 18 dopant atoms per cm 3 . At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

First claim

What is claimed is:

1. A field effect transistor structure having a gate dielectric under a gate with length Lg, comprising:
a substrate,
a well in the substrate doped to have a first concentration of a first conductivity type dopant,
a substantially undoped channel under the gate dielectric and extending to a source and a drain, the source and the drain being doped to have a second conductivity type dopant different from the first conductivity type dopant, the substantially undoped channel having a second concentration of the first conductivity type dopant less than the first concentration,
a screening region positioned above the well and under the gate dielectric, the screening region extending to the source and drain and having a third concentration of the first conductivity type dopant, the screening region setting a depth of a depletion region below the gate in a direction from the substantially undoped channel toward the screening region, a ratio of the third concentration to the second concentration being more than ten, a profile of the first conductivity type dopant having a peak in the screening region,
at least one punch through suppression region having a fourth concentration of the first conductivity type dopant intermediate between the first concentration and the third concentration, with the punch through suppression region positioned above the well and beneath the screening region, and
a threshold voltage set region having a fifth concentration of the first conductivity type dopant intermediate between the second concentration and the third concentration, with the threshold voltage set region positioned under the substantially undoped channel and above the screening region, the threshold voltage set region extending to the source and drain.

2. The field effect transistor structure of claim 1 , wherein the screening region is positioned at a depth below the gate dielectric of between about Lg/5 and about Lg/1.

3. The field effect transistor structure of claim 1 , wherein the channel is formed as a blanket epitaxial layer.

4. The field effect transistor structure of claim 1 , wherein the punch through suppression region has a dopant concentration different from the screening region.

5. The field effect transistor structure of claim 1 , wherein each of the screening region and the punch through suppression region establishes a notch in the profile of the first conductivity type dopant.

6. The field effect transistor structure of claim 1 , wherein the third concentration is larger than the fourth concentration and the fifth concentration, the fourth concentration is larger than the first concentration.

7. The field effect transistor structure of claim 1 , wherein the depletion region does not go through the screening region, regardless of a voltage of the well when a voltage of the gate equals to the threshold voltage.

8. The field effect transistor structure of claim 1 , wherein there is not a local minimum between the threshold voltage set region and the screening region in the profile of the first conductivity type dopant.

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Shifren Lucian
• Ranade Pushkar
• Gregory Paul E
• Sonkusale Sachin R
• Zhang Weimin
• Thompson Scott E

Classifications

• H01L27/092

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic

• H01L29/7833

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic

• H01L21/823412

  Electricity · mapped topic