Advanced transistors with punch through suppression

Patent metadata

Field	Value
Publication number	US-9508800-B2
Application number	US-201514977887-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Sep 30, 2009
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×10 18 dopant atoms per cm 3 . At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

First claim

What is claimed is:

1. A die, comprising:
a substrate that is a single crystal of semiconductor material;
a first field effect transistor structure and a second field effect transistor structure, each supported by the substrate;
wherein the first field effect transistor structure has a first gate, a first source, a first drain, and a first plurality of distinct doped regions underlying the first gate and extending between the first source and the first drain, the first plurality of doped regions implanted to define a first dopant profile of p-type, the first dopant profile having a p-type peak dopant concentration at a first depth from the first gate, a first p-type intermediate dopant concentration at a second depth from the first gate, the first p-type intermediate dopant concentration being lower than the p-type peak dopant concentration;
wherein the first field effect transistor structure includes a first channel region formed by an undoped blanket epitaxial growth, the first channel region being directly on a first threshold voltage control region formed in the single crystal of the single semiconductor material, the first threshold voltage control region associated with the first intermediate dopant concentration,
wherein the second field effect transistor structure has a second gate, a second source, a second drain, and a second plurality of distinct doped regions underlying the second gate and extending between the second source and the second drain, the second plurality of doped regions implanted to define a second dopant profile of n-type, the second dopant profile having a n-type peak dopant concentration at a third depth from the second gate, a first n-type intermediate dopant concentration at a fourth depth from the second gate, the first n-type intermediate dopant concentration being lower than the n-type peak dopant concentration;
wherein the second field effect transistor structure includes a second channel region commonly formed by the undoped blanket epitaxial growth, the second channel region being directly on a second threshold voltage control region formed in the single crystal of the single semiconductor material, the second threshold voltage control region associated with the first n-type intermediate dopant concentration.

2. The die of claim 1 , wherein the first dopant profile includes a second p-type intermediate dopant concentration at a fifth depth from the first gate, the second p-type intermediate dopant concentration is higher than the first p-type intermediate dopant concentration, wherein the second dopant profile includes a second n-type intermediate dopant concentration at a sixth depth from the second gate, the second n-type intermediate dopant concentration is higher than the first n-type intermediate dopant concentration.

3. The die of claim 1 , wherein the p-type peak dopant concentration at the first depth sets a first depletion depth for the first field effect transistor structure when a first voltage is applied to the first gate, wherein the n-type peak dopant concentration at the third depth sets a second depletion depth for the second field effect transistor structure when a second voltage is applied to the second gate.

4. The die of claim 1 , further comprising:
a first bias structure coupled to the first source of the first field effect transistor structure, the first bias structure operable to modify a first operational threshold voltage of the first field effect transistor structure, a second bias structure coupled to the second source of the second field effect transistor structure, the second bias structure operable to modify a second operational threshold voltage of the second field effect transistor structure.

5. The die of claim 4 , further comprising:
a first fixed voltage source coupled to the first bias structure to statically set the first threshold voltage of the first field effect transistor structure and a second fixed voltage source coupled to the second bias structure to statically set the second threshold voltage of the second field effect transistor structure.

6. The die of claim 4 , further comprising:
a first variable voltage source coupled to the first bias structure to dynamically adjust the first threshold voltage of the first field effect transistor structure and a second variable voltage source coupled to the second bias structure to dynamically adjust the second threshold voltage of the second field effect transistor structure.

7. The die of claim 4 , wherein the first field effect transistor structure and the second field effect transistor structure are separated into different bias sections, a first bias section providing no threshold voltage adjustment, a second bias section operable to provide static threshold voltage adjustment, and a third bias section operable to provide dynamic threshold voltage adjustment.

8. The die of claim 7 , wherein the different bias sections have different threshold voltages with or without any adjustment.

9. The die of claim 1 , wherein the first depth is deeper below the first gate than the second depth, the third depth is deeper below the second gate than the fourth depth.

10. The die of claim 1 , wherein the first depth is in a range between one half and one fifth of a length of the first gate and the third depth is in a range between one half and one fifth of a length of the second gate.

11. The die of claim 1 , wherein each of the first plurality of doped regions and the second plurality of doped regions are formed in the substrate.

12. The die of claim 1 , wherein each of the first plurality of doped regions and the second plurality of doped regions are formed on the substrate.

13. The die of claim 1 , further comprising:
first source and drain extensions extending into the first channel region of the first field effect transistor structure and second source and drain extensions extending into the second channel region of the second field effect transistor structure.

14. The die of claim 1 , wherein the first plurality of doped regions are in contact with the first source and the first drain and the second plurality of doped regions are in contact with the second source and the second drain.

15. The die of claim 1 , wherein the first dopant profile has a first dopant concentration at a first point between the first depth and the second depth, the first dopant concentration being less than or equal to the first p-type intermediate dopant concentration to establish a first p-type notch in the first dopant profile, the second dopant profile has a second dopant concentration at a second point between the third depth and the fourth depth, the second dopant concentration being less than or equal to the first n-type intermediate dopant concentration to establish a first n-type notch in the second dopant profile.

16. The die of claim 2 , wherein the first dopant profile has a third dopant concentration at a third point between the first depth and the fifth depth, the third dopant concentration being less than or equal to the second p-type intermediate dopant concentration to establish a second p-type notch in the first dopant profile, the second dopant profile has a fourth dopant concentration at a fourth point between the third depth and the sixth depth, the fourth dopant concentration being less than or equal to the second n-type intermediate dopant concentration to establish a second n-type notch in the second dopant profile.

17. The die of claim 2 , wherein the second p-type intermediate dopant concentration is associated with a p-type suppression of punch through region of

Assignees

• Mie Fujitsu Semiconductor Ltd

Inventors

• Shifren Lucian
• Ranade Pushkar
• Gregory Paul E
• Sonkusale Sachin R
• Zhang Weimin
• Thompson Scott E

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D30/605

  having significant overlap between the lightly-doped extensions and the gate electrode · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title