Efficient and selective sparing of bits in memory systems
US-11698842-B2 · Jul 11, 2023 · US
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Maule Warren E patents
Maule Warren E is listed as an inventor on 136 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Maule Warren E |
| Total patents | 136 |
| First publication | Mar 26, 2015 |
| Latest publication | Jul 11, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel
US-11593196-B2 · Feb 28, 2023 · US
Hybrid memory mirroring using storage class memory
US-11586360-B2 · Feb 21, 2023 · US
Address/command chip controlled data chip address sequencing for a distributed memory buffer system
US-11587600-B2 · Feb 21, 2023 · US
Hybrid memory mirroring using storage class memory
US-2022365685-A1 · Nov 17, 2022 · US
Method and apparatus to reduce bandwidth overhead of crc protection on a memory channel
US-2022091927-A1 · Mar 24, 2022 · US
Redundant voltage regulator for memory devices
US-11264077-B2 · Mar 1, 2022 · US
Efficient and selective sparing of bits in memory systems
US-2022027243-A1 · Jan 27, 2022 · US
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel
US-11200112-B1 · Dec 14, 2021 · US
Efficient and selective sparing of bits in memory systems
US-11182262-B2 · Nov 23, 2021 · US
Recent patents
Latest publications not already listed above.
Using dual channel memory as single channel memory with spares
US-11037619-B2 · Jun 15, 2021 · US
Tracking address ranges for computer memory errors
US-11017875-B2 · May 25, 2021 · US
Redundant voltage regulator for memory devices
US-2021134346-A1 · May 6, 2021 · US
Performing error correction in computer memory
US-10971246-B2 · Apr 6, 2021 · US
Redundant voltage regulator for memory devices
US-10937485-B2 · Mar 2, 2021 · US
Common high and low random bit error correction logic
US-10901839-B2 · Jan 26, 2021 · US
Common high and low random bit error correction logic
US-10824504-B2 · Nov 3, 2020 · US
Host controlled data chip address sequencing for a distributed memory buffer system
US-10747442-B2 · Aug 18, 2020 · US
Efficient and selective sparing of bits in memory systems
US-2020226040-A1 · Jul 16, 2020 · US
Efficient and selective sparing of bits in memory systems
US-10671497-B2 · Jun 2, 2020 · US
Autonomous dram scrub and error counting
US-10628248-B2 · Apr 21, 2020 · US
Memory mirror invocation upon detecting a correctable error
US-10613951-B2 · Apr 7, 2020 · US
Using dual channel memory as single channel memory with command address recovery
US-10606713-B2 · Mar 31, 2020 · US
Error correction potency improvement via added burst beats in a dram access cycle
US-10606692-B2 · Mar 31, 2020 · US
Common high and low random bit error correction logic
US-2020097359-A1 · Mar 26, 2020 · US
Auto-disabling DRAM error checking on threshold
US-10592332-B2 · Mar 17, 2020 · US
Using dual channel memory as single channel memory with spares
US-2020075079-A1 · Mar 5, 2020 · US
Using dual channel memory as single channel memory with spares
US-10546628-B2 · Jan 28, 2020 · US
Three-dimensional stacked memory optimizations for latency and power
US-10534545-B2 · Jan 14, 2020 · US
Redundant voltage regulator for memory devices
US-2020013449-A1 · Jan 9, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 137 |
| Globalfoundries Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F11/1048 | 64 |
| G11C29/52 | 33 |
| G06F3/0619 | 33 |
| G06F11/1068 | 26 |
| G06F3/0673 | 26 |