Three-dimensional stacked memory optimizations for latency and power

Patent metadata

Field	Value
Publication number	US-10534545-B2
Application number	US-201715847954-A
Country	US
Kind code	B2
Filing date	Dec 20, 2017
Priority date	Dec 20, 2017
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.

First claim

What is claimed is:

1. A method comprising:
receiving a request to write data to a memory, the memory comprising a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV), the request to write data received by a hypervisor from an application executing on a virtual machine managed by the hypervisor; and
in response to receiving the request:
determining a latency requirement of accesses to the write data;
determining one or more positions in the stack of memory devices for the write data based at least in part on the latency requirement and a predicted power consumption of the write data;
assigning a physical location for the write data on a memory device located at one of the one or more positions in the stack of memory devices; and
sending a write command to a memory controller, the write command including the physical location and the write data.

2. The method of claim 1 , wherein the request includes a tag that specifies the latency requirement.

3. The method of claim 1 , further comprising determining a predicted access frequency of the write data, wherein the determining one or more positions in the stack of memory devices for the write data is further based at least in part on the predicted access frequency of the write data.

4. The method of claim 1 , further comprising determining a predicted length of time that the write data will be stored in the memory, wherein the determining one or more positions in the stack of memory devices for the write data is further based at least in part on the predicted length of time that the write data will be stored in the memory.

5. The method of claim 1 , wherein the memory devices are homogenous.

6. The method of claim 1 , wherein the memory devices are heterogeneous.

7. The method of claim 6 , wherein the assigning is based at least in part on a type of the memory device.

8. The method of claim 6 , wherein the memory devices are placed in the stack in an order that is based on a thermal characteristic of at least one of the memory devices in the stack.

9. The method of claim 6 , wherein the memory devices are placed in the stack in an order that is based on an access speed of at least one of the memory devices in the stack.

10. A system comprising:
a first memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
receiving a request to write data to a second memory, the second memory comprising a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV), the request to write data received by a hypervisor from an application executing on a virtual machine managed by the hypervisor; and
in response to receiving the request:
determining a latency requirement of accesses to the write data;
determining one or more positions in the stack of memory devices for the write data based at least in part on the latency requirement and a predicted power consumption of the write data;
assigning a physical location for the write data on a memory device located at one of the one or more positions in the stack of memory devices; and
sending a write command to a memory controller, the write command including the physical location and the write data.

11. The system of claim 10 , wherein the request includes a tag that specifies the latency requirement.

12. The system of claim 10 , wherein the operations further comprise determining a predicted access frequency of the write data, wherein the determining one or more positions in the stack of memory devices for the write data is further based at least in part on the predicted access frequency of the write data.

13. The system of claim 10 , wherein the operations further comprise determining a predicted length of time that the write data will be stored in the second memory, wherein the determining one or more positions in the stack of memory devices for the write data is further based at least in part on the predicted length of time that the write data will be stored in the second memory.

14. The system of claim 10 , wherein the memory devices are homogenous.

15. The system of claim 10 , wherein the memory devices are heterogeneous.

16. The system of claim 15 , wherein the assigning is based at least in part on a type of the memory device.

17. The system of claim 15 , wherein the memory devices are placed in the stack in an order that is based on a thermal characteristic of at least one of the memory devices in the stack.

18. The system of claim 15 , wherein the memory devices are placed in the stack in an order that is based on an access speed of at least one of the memory devices in the stack.

19. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
receiving a request to write data to a memory, the memory comprising a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV), the request to write data received by a hypervisor from an application executing on a virtual machine managed by the hypervisor; and
in response to receiving the request:
determining a latency requirement of accesses to the write data;
determining one or more positions in the stack of memory devices for the write data based at least in part on the latency requirement and a predicted power consumption of the write data;
assigning a physical location for the write data on a memory device located at one of the one or more positions in the stack of memory devices; and
sending a write command to a memory controller, the write command including the physical location and the write data.

20. The computer program product of claim 19 , wherein the request includes a tag that specifies the latency requirement.

Assignees

• IBM

Inventors

• Chinnakkonda Vidyapoornachary Diyanesh B
• Deforge John B
• Maule Warren E
• Peterson Kirk D
• Rangarajan Sridhar H
• Sethuraman Saravanan

Classifications

• G11C29/50012

  of timing · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/025

  in signal lines · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title