Performing error correction in computer memory

Patent metadata

Field	Value
Publication number	US-10971246-B2
Application number	US-201916387846-A
Country	US
Kind code	B2
Filing date	Apr 18, 2019
Priority date	Sep 2, 2016
Publication date	Apr 6, 2021
Grant date	Apr 6, 2021

Abstract

Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.

First claim

What is claimed is:

1. A method of performing error correction in computer memory, the method comprising:
receiving a read request targeting a read address within the computer memory;
accessing a mark table comprising a plurality of entries, each entry corresponding to a detected error at a memory address in a physical location of computer memory, each entry including a field specifying a memory region size identifying a hierarchical memory level within the computer memory, a field specifying a match address, and a field specifying a mark location;
performing a lookup of the mark table using the read address including, for each entry in the mark table:
generating a mask based on the memory region size stored in the entry;
determining, based on the mask, whether the read address is within a memory region specified by the match address and memory region size stored in the entry; and
if the read address is within the memory region specified by the match address and memory region size stored in the entry, performing error correction using the mark location stored in the entry.

2. The method of claim 1 , wherein the mark table is stored in content addressable memory (CAM), and wherein the lookup is a CAM lookup.

3. The method of claim 1 , wherein generating the mask based on the memory region size stored in the entry comprises:
accessing an entry in a mask-generation table corresponding to the memory region size stored in the entry; and
retrieving the mask from the entry in the mask-generation table.

4. The method of claim 1 , wherein determining, based on the mask, whether the read address is within the memory region specified by the match address and memory region size stored in the entry comprises:
applying an XOR operation to the read address and the match address to obtain a result address;
applying the mask to the result address to obtain a masked result address; and
determining whether the masked result address is equal to zero.

5. The method of claim 1 , wherein the memory region is one selected from a group consisting of a dual in-line memory module (DIMM), a rank, a bank group, and a bank.

6. The method of claim 1 , wherein the field specifying the mark location indicates at least one of a group consisting of a chip mark and a symbol mark.

7. An apparatus for performing error correction in computer memory, the apparatus comprising memory firmware and a mark table, the apparatus configured to carry out the steps of:
receiving, by the memory firmware, a read request targeting a read address within the computer memory;
accessing, by the memory firmware, the mark table comprising a plurality of entries, each entry corresponding to a detected error at a memory address in a physical location of computer memory, each entry including a field specifying a memory region size identifying a hierarchical memory level within the computer memory, a field specifying a match address, and a field specifying a mark location;
performing, by the memory firmware, a lookup of the mark table using the read address including, for each entry in the mark table:
generating a mask based on the memory region size stored in the entry;
determining, based on the mask, whether the read address is within a memory region specified by the match address and memory region size stored in the entry; and
if the read address is within the memory region specified by the match address and memory region size stored in the entry, performing error correction using the mark location stored in the entry.

8. The apparatus of claim 7 , wherein the mark table is stored in content addressable memory (CAM), and wherein the lookup is a CAM lookup.

9. The apparatus of claim 7 , wherein generating the mask based on the memory region size stored in the entry comprises:
accessing an entry in a mask-generation table corresponding to the memory region size stored in the entry; and
retrieving the mask from the entry in the mask-generation table.

10. The apparatus of claim 7 , wherein determining, based on the mask, whether the read address is within the memory region specified by the match address and memory region size stored in the entry comprises:
applying an XOR operation to the read address and the match address to obtain a result address;
applying the mask to the result address to obtain a masked result address; and
determining whether the masked result address is equal to zero.

11. The apparatus of claim 7 , wherein the memory region is one selected from a group consisting of a dual in-line memory module (DIMM), a rank, a bank group, and a bank.

12. The apparatus of claim 7 , wherein the field specifying the mark location indicates at least one of a group consisting of a chip mark and a symbol mark.

13. A computer program product for performing error correction in computer memory, the computer program product comprising a non-transitory computer readable storage medium having computer program instructions embodied therewith that, when executed, cause a computer to carry out the steps of:
receiving a read request targeting a read address within the computer memory;
accessing a mark table comprising a plurality of entries, each entry corresponding to a detected error at a memory address in a physical location of computer memory, each entry including a field specifying a memory region size identifying a hierarchical memory level within the computer memory, a field specifying a match address, and a field specifying a mark location;
performing a lookup of the mark table using the read address including, for each entry in the mark table:
generating a mask based on the memory region size stored in the entry;
determining, based on the mask, whether the read address is within a memory region specified by the match address and memory region size stored in the entry; and
if the read address is within the memory region specified by the match address and memory region size stored in the entry, performing error correction using the mark location stored in the entry.

14. The computer program product of claim 13 , wherein the mark table is stored in content addressable memory (CAM), and wherein the lookup is a CAM lookup.

15. The computer program product of claim 13 , wherein generating the mask based on the memory region size stored in the entry comprises:
accessing an entry in a mask-generation table corresponding to the memory region size stored in the entry; and
retrieving the mask from the entry in the mask-generation table.

16. The computer program product of claim 13 , wherein determining, based on the mask, whether the read address is within the memory region specified by the match address and memory region size stored in the entry comprises:
applying the mask to the read address and the match address to obtain a masked read address and a masked match address; and
determining whether the masked read address and the masked match address are equal.

17. The computer program product of claim 13 , wherein determining, based on the mask, whether the read address is within the memory region specified by the match address and memory region size stored in the entry comprises:
applying an XOR operation to the read address and the match address to obtain a result address;
applying the mask to the result address to obtain a masked result address; and
determining whether the masked result address is equal to zero.

18. The computer program product of claim 13 , wherein the memory region is one selected from a group consisting of a dual in-line memory module (DIMM), a rank, a b

Assignees

• IBM

Inventors

• Dodson John S
• Gollub Marc A
• Maule Warren E
• Michael Brad W

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F11/1064

  in cache or content addressable memories · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title