Efficient and selective sparing of bits in memory systems

Patent metadata

Field	Value
Publication number	US-10671497-B2
Application number	US-201815875136-A
Country	US
Kind code	B2
Filing date	Jan 19, 2018
Priority date	Jan 19, 2018
Publication date	Jun 2, 2020
Grant date	Jun 2, 2020

Abstract

A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.

First claim

What is claimed is:

1. A memory system for storing data, the memory system comprising:
a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together to respond to a request;
a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices;
a detector for detecting a bit error in an operation; and
a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error,
wherein the memory control circuit is configured to read data in a spare bit in the spare bit lane and location information in the spare bit lane to identify where to use the data in the spare bit in the spare bit lane.

2. The system of claim 1 wherein the detector, the controller, and the memory control circuit are on the same chip.

3. The system of claim 1 , wherein the plurality of memory devices is on a dual inline memory module (DIMM), the memory control circuit is on the DIMM, and the DIMM further comprises a plurality of data buffer circuits.

4. The system of claim 3 , wherein the DIMM comprises the plurality of memory devices, wherein a first subset of the memory devices form a first rank and a second subset of memory devices form a second rank, and further wherein thirty-two bits per rank are used to store data.

5. The system of claim 4 , wherein at least one bit lane is use for remapping the bit error.

6. The system of claim 4 , further comprising rewriting information to a particular spare bit in the spare bit lane, wherein the information rewritten to the particular spare bit includes data of the bit where the error was detected, a location of the bit where the error was detected, and an error correction code for the particular spare bit.

7. The subsystem of claim 1 , where the plurality of memory devices provides a plurality of spare bit lanes to remap bit errors.

8. A memory system for storing data, the memory system comprising:
a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together to perform an operation;
a memory control circuit associated with the plurality of memory devices, and configured to output signals to the plurality of memory devices, the memory control circuit containing logic circuits configured to (i) detect a failing bit during an operation; (ii) rewrite data from the failing bit to a single spare bit lane; and (iii) read the data rewritten to the spare bit lane for the failing bit,
wherein the memory control circuit is configured to write a location address of the failing bit to the spare bit lane.

9. The memory system of claim 8 , further comprising an error correction code (ECC) for the data and the location information address written to the spare bit lane.

10. A method for managing bit errors in a memory subsystem, the method comprising:
detecting a first error in a first memory bit location in a plurality of memory devices in a first operation; and
remapping data to be stored at the first memory bit location where the first error was detected to a spare bit lane,
wherein during a read operation valid data is read from the spare bit lane, wherein the valid data comprises a bit of data, one or more bits of location information for said bit of data, and one or more bits of error correction code protecting said data bit and one or more bits of the location information.

11. The method of claim 10 , wherein the data to be stored at the first memory bit location where the first error was detected is remapped to a spare bit in the spare bit lane.

12. The method of claim 11 , wherein the remapping includes storing location information identifying the location of the first error and an error correction code for the spare bit in the spare bit lane.

13. The method of claim 10 , wherein a single error in the first operation is written to a single bit lane.

14. The method of claim 10 , wherein the first operation is a read operation and an error is detected during the read operation, the method further comprising performing a write operation wherein a memory controller writes information in the spare bit lane to a memory bit location identified by location information contained in the spare bit lane.

15. The method of claim 10 , wherein during a read operation particular valid data is read from the spare bit lane, wherein the particular valid data comprises one spare bit that is remapped into the read particular valid data by a memory controller using location information stored in the spare bit lane to reconstruct original non-spared data.

16. The method of claim 10 , further comprising:
detecting a second error in a bit memory location in a different operation, the second error occurring in a second memory bit location in at least one of the group consisting of a same memory bit location as the first error and a different memory bit location; and
remapping data to be stored at the second memory bit location where the second error was detected to a single spare bit lane in the different operation.

17. The method of claim 10 , further comprising providing a plurality of memory devices, wherein a plurality of bits are configured to store data, a plurality of bits are for an error correction code, and at least one bit is for managing error correction.

Assignees

• IBM

Inventors

• Glancy Stephen
• Kim Kyu-Hyoun
• Maule Warren E
• Mcilvain Kevin M

Classifications

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C2029/1204

  Bit line control · CPC title

• G11C29/76 Primary

  using address translation or modifications · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title