Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel

Patent metadata

Field	Value
Publication number	US-11593196-B2
Application number	US-202117539813-A
Country	US
Kind code	B2
Filing date	Dec 1, 2021
Priority date	Aug 24, 2020
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

First claim

What is claimed is:

1. A non-transitory computer readable medium comprising instructions that, in response to being executed by at least one hardware processor, cause the processor to:
select information on a per memory device basis to associate with one or more spare memory devices in a memory system, wherein the memory system has a plurality of memory devices, at least one or more of the plurality of memory devices configured as a data memory device to store data and at least one or more of the plurality of memory devices are configured as a spare memory device;
disassociating the selected information from one or more data memory devices leaving remaining information on the one or more data memory devices;
associating the selected information with one or more spare memory devices;
adding Cyclical Redundancy Check (CRC) code to the remaining information on the one or more data memory devices from which the selected information was disassociated; and
transferring the CRC code and the remaining information over a bus between a host and the memory system.

2. The non-transitory computer readable medium of claim 1 , further comprising instructions that, in response to being executed by at least one hardware processor, cause the processor to check the bus between the host and the memory system.

3. The non-transitory computer readable medium of claim 1 , wherein the selected information is data from one or more of the data memory devices and the selected data is associated with one or more of the spare memory devices.

4. The non-transitory computer readable medium of claim 1 , wherein the plurality of memory devices are configured as a single channel having an interface width wherein one or more bits of the interface width communicate with one or more data memory devices, one or more bits of the interface width communicate with one or more memory devices configured to handle error correction code (ECC), and one or more bits communicate with one or more spare memory devices, and further comprising instructions that, in response to being executed by at least one hardware processor, cause the processor to select at least two bursts of data from at least one data memory device to be associated with the one or more spare memory devices.

5. The non-transitory computer readable medium of claim 4 , further comprising instructions that, in response to being executed by at least one hardware processor, cause the processor to select at least two bursts of data from at least four data memory devices to be associated with the one or more spare memory devices.

6. The non-transitory computer readable medium of claim 1 , further comprising instructions that, in response to being executed by at least one hardware processor, cause the processor to:
transfer the selected information, the remaining information and the CRC code from the plurality of memory devices over the bus to the host;
check the CRC code transferred over the bus;
discard the CRC code transferred over the bus; and
obtain the selected information transferred over the bus to the host.

7. The non-transitory computer readable medium of claim 1 , further comprising instructions that, in response to being executed by at least one hardware processor, cause the processor to:
check the CRC code transferred over the bus between the host and the memory system;
discard the CRC code transferred over the bus;
transfer the selected information over the bus from the one or more spare devices to the host;
transfer the remaining information over the bus from the one or more data memory devices;
obtain the selected information transferred from the one or more spare memory devices to the host; and
combine the selected information transferred from the one or more spare memory devices with the remaining information transferred from the one or more data memory devices.

8. The non-transitory computer readable medium of claim 1 , further comprising instructions that, in response to being executed by at least one hardware processor, cause the processor to:
transfer the remaining information, the selected information, and CRC code from the host over the bus to the plurality of memory devices including at least one of the spare memory devices;
check, by the memory device that receives the CRC code, the CRC code transferred over the bus to the memory device that receives the CRC code;
save the remaining information, the selected information, and the CRC code in the plurality of memory devices and at least one of the spare memory devices.

9. An information handling system, the information handling system comprising:
a memory subsystem comprising a plurality of memory devices, the plurality of memory devices including a group of data memory devices configured to store data and at least one spare memory device;
a processor having a memory controller for controlling the transfer of information between the processor and the memory subsystem;
a bus between the processor and the memory subsystem, the bus comprising one or more data lanes for transferring information between the processor and each of the plurality of memory devices in the memory subsystem, the information handling system configured to:
select information on a per memory device basis for transfer to the group of data memory devices to associate with one or more of the spare memory devices;
disassociate the selected information for transfer from the group of data memory devices leaving remaining information;
associate the selected information with the one or more of the spare memory devices;
add Cyclical Redundancy Check (CRC) code to the remaining information; and
transfer the CRC code and the remaining information over the bus between the processor and the plurality of memory subsystem.

10. The information handling system of claim 9 , wherein the system is further configured to:
check the bus between the processor and the one or more memory devices that received the CRC code.

11. The information handling system of claim 9 , wherein the system is further configured to:
select data from one or more of the data memory devices and associate the selected data with the one or more spare memory devices.

12. The information handling system of claim 9 , wherein the plurality of memory devices are configured as a single channel having an interface width wherein one or more bits of the interface width communicate with the group of data memory devices, one or more bits of the interface width communicate with one or more memory devices configured to handle error correction code (ECC), and one or more bits of the interface communicate with one or more memory devices configured as the at least one spare memory device, and wherein the system is further configured to select at least two bursts of data from at least one of the group of data memory devices to be associated with the one or more spare memory devices.

13. The information handling system of claim 12 , wherein the system is further configured to select at least two bursts of data from at least four data memory devices from the group of data memory devices to be associated with the one or more spare memory devices.

14. The information handling system of claim 9 , wherein the system is further configured:
transfer the remaining information, the selected information, and the CRC code from the plurality of memory devices over the bus to the processor;
check the CRC code transferred over the bus;
discard the CRC code transferred over the bus;
obtain the selected information transferred over the bus; and
combine the selected information transferred over the bus with the remaining inform

Assignees

• IBM

Inventors

• Mcilvain Kevin M
• Maule Warren E
• Glancy Stephen
• Kim Kyu-Hyoun
• Cordero Edgar R

Classifications

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title