Using dual channel memory as single channel memory with spares

Patent metadata

Field	Value
Publication number	US-11037619-B2
Application number	US-201916674235-A
Country	US
Kind code	B2
Filing date	Nov 5, 2019
Priority date	Jan 3, 2018
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

First claim

What is claimed is:

1. A method for operating a memory controller, the method comprising:
driving first memory devices and second memory devices of the memory controller in a dual channel mode, a first error correcting code (ECC) memory device and a second ECC memory device protecting the first memory devices and the second memory devices; and
driving the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device having been disabled for error correction, the first ECC memory device protecting the first memory devices and the second memory devices in the single channel mode, the memory controller being configured to disable the second ECC memory device during the single channel mode such that the second ECC memory device is the spare memory device.

2. The method of claim 1 , wherein the first memory devices and the second memory devices are dynamic random access memory (DRAM).

3. The method of claim 1 , wherein the first memory devices and the second memory devices are a DRAM dual in-line memory module (DIMM).

4. The method of claim 1 , wherein:
the first memory devices comprise first data memory devices configured for data storage and the first ECC memory device configured for error correction; and
the second memory devices comprise second data memory devices configured for data storage and the second ECC memory device configured for error correction.

5. The method of claim 4 , wherein:
the memory controller is configured to detect a failed memory device from the first memory devices and the second memory devices; and
the memory controller is configured to replace the failed memory device with the spare memory device such that the spare memory device operates in place of the failed memory device.

6. The method of claim 5 , wherein, in response to detecting the failed memory device, the memory controller is configured to cause the spare memory device to operate in place of any one of the first data memory devices, the first ECC memory device, and the second memory devices.

7. The method of claim 4 , wherein the first data memory devices have a 32-bit wide data interface and the second data memory devices have another 32-bit wide data interface.

8. The method of claim 7 , wherein, during the single channel mode, the memory controller is configured to cause the first ECC memory device to protect a 64-bit wide data interface for both the first data memory devices and the second data memory devices, the 64-bit wide data interface comprising the 32-bit wide data interface and the another 32-bit wide data interface.

9. The method of claim 1 , wherein the first ECC memory device is 8-bits.

10. A memory controller comprising:
a circuit configured to control a memory module, the circuit being configured to:
drive first memory devices and second memory devices of the memory controller in a dual channel mode, a first error correcting code (ECC) memory device and a second ECC memory device protecting the first memory devices and the second memory devices; and
drive the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device having been disabled for error correction, the first ECC memory device protecting the first memory devices and the second memory devices in the single channel mode the circuit being configured to disable the second ECC memory device during the single channel mode such that the second ECC memory device is the spare memory device.

11. The memory controller of claim 10 , wherein the first memory devices and the second memory devices are dynamic random access memory (DRAM).

12. The memory controller of claim 10 , wherein the memory module is a DRAM dual in-line memory module (DIMM).

13. The memory controller of claim 10 , wherein:
the first memory devices comprise first data memory devices configured for data storage and the first ECC memory device configured for error correction; and
the second memory devices comprise second data memory devices configured for data storage and the second ECC memory device configured for error correction.

14. The memory controller of claim 13 , wherein: the circuit is configured to detect a failed memory device from the first memory devices and the second memory devices; the circuit is configured to replace the failed memory device with the spare memory device such that the spare memory device operates in place of the failed memory device; and in response to detecting the failed memory device, the circuit is configured to cause the spare memory device to operate in place of any one of the first data memory devices, the first ECC memory device, and the second memory devices.

15. The memory controller of claim 13 , wherein the first data memory devices have a 32-bit wide data interface and the second data memory devices have another 32-bit wide data interface.

16. The memory controller of claim 15 , wherein, during the single channel mode, the circuit is configured to cause the first ECC memory device to protect a 64-bit wide data interface for both the first data memory devices and the second data memory devices, the 64-bit wide data interface comprising the 32-bit wide data interface and the another 32-bit wide data interface.

17. The memory controller of claim 13 , wherein the first ECC memory device is 8 bits.

18. A method of switching from dual channel mode to single channel mode, the method comprising:
determining that a switch is needed from the dual channel mode to the single channel mode of operating a memory module, the memory module comprising memory devices on a first channel and a second channel; and
switching from the dual channel mode to the single channel mode, which comprises causing a spare error correcting code (ECC) memory device of the memory devices to be available by protecting the first and second channels with a single ECC memory device instead of two ECC memory devices of the memory devices, a second ECC memory device of the two ECC memory devices being configured to be switched from protecting the first and second channels to operating as one of the memory devices via commands from a register clock driver (RCD).

Assignees

• IBM

Inventors

• Kim Kyu-Hyoun
• Maule Warren E
• Mcilvain Kevin M
• Sethuraman Saravanan

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/74

  using duplex memories, i.e. using dual copies · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title