Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Patent metadata

Field	Value
Publication number	US-11587600-B2
Application number	US-201916397154-A
Country	US
Kind code	B2
Filing date	Apr 29, 2019
Priority date	Nov 29, 2017
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. The memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.

First claim

What is claimed is:

1. A method for storing data in memory devices, the method comprising:
processing, by a memory module containing a memory control circuit, at least one data buffer circuit, and the memory devices, a store command in the memory control circuit into a write-to-buffer command and a store-from-buffer command;
sending the write-to-buffer command and a store data tag from the memory control circuit to the at least one data buffer circuit; and
pushing incoming data into a location in the at least one data buffer circuit pointed to by the store data tag obtained from the memory control circuit.

2. The method of claim 1 , wherein the at least one data buffer circuit pushes incoming data into the at least one data buffer circuit in response to receiving the write-to-buffer command.

3. The method of claim 2 , further comprising:
sending a store command from the memory control circuit to the memory devices;
sending the store-from-buffer command along with the store data tag to the at least one data buffer circuit; and
sending data from the location in the at least one data buffer circuit pointed to by the store data tag to the memory devices.

4. The method of claim 3 , wherein the at least one data buffer circuit receives the data store tag over a third link between the memory control circuit and the at least one data buffer circuit.

5. The method of claim 3 , further comprising the step of returning the store data tag back to a host.

6. The method of claim 3 , wherein the data buffer circuit receives the store data tag and the store from buffer command over a third communications link between the memory control circuit and the at least one data buffer circuit.

7. The method of claim 3 , wherein the store command is sent from the memory control circuit to the memory devices over a fourth communications link.

8. The method of claim 3 , wherein data is sent from the at least one data buffer circuit to the memory devices over a fifth communications link.

9. The method of claim 1 , wherein the at least one data buffer circuit receives the incoming data over a second communications link between a host and the at least one data buffer circuit, but no store data tag is received by the at least one data buffer circuit from the host over the second communications link between the host and the at least one data buffer circuit.

10. The method of claim 1 , further comprising the memory control circuit receiving the store command and the store data tag from a host.

11. The method of claim 10 , wherein the memory control circuit receives the store command and the store data tag from the host over a first communications link.

12. A method for storing data in memory devices, the method comprising:
receiving a store command along with a store data tag from a host tag pool over a first communications link into a memory control circuit;
decoding the store command in the memory control circuit into a write-to-buffer command and a store-from-buffer command;
sending the write-to-buffer command along with the store data tag over a third communications link to the data buffer circuit; and
in response to receiving the write-to-buffer command, the data buffer circuit receives incoming data over a second communications link into a location in the data buffer circuit pointed to by the store data tag received from the memory control circuit.

13. The method of claim 12 , further comprising the memory control circuit pushing the store-from-buffer command with the store data tag into a store command FIFO buffer.

14. The method of claim 13 , further comprising sending the store command from the memory control circuit over a fourth communications link to the memory devices, and sending the store-from-buffer command along with the store data tag over the third communications link to the data buffer circuit.

15. The method of claim 14 , further comprising moving the data out of the location in the data buffer circuit pointed to by the store data tag and sending the data in response to the data buffer circuit receiving the store-from-buffer command from the data buffer circuit over a fifth communications link to the memory devices.

16. The method of claim 14 , further comprising returning the store data tag to the host over the first communications link.

17. The method of claim 16 , further comprising returning the store data tag back to the host tag pool.

18. A method for storing data in memory devices, the method comprising:
receiving a store command along with a store data tag over a first communications link into a memory control circuit;
decoding the store command in the memory control circuit into a write-to-buffer command and a store-from-buffer command;
sending the store-from-buffer command along with the store data tag into a store command FIFO buffer;
sending the write-to-buffer command along with store data tag from the memory control circuit over a third communications link to the data buffer circuit;
in response to receiving the write-to-buffer command, the data buffer circuit receives incoming data over a second communications link into a location in the data buffer circuit pointed to by the store data tag received from the memory control circuit; and
sending the incoming data from the location in the data buffer circuit pointed to by the store data tag over a fifth communications link to the memory devices.

19. The method of claim 18 , further comprising the memory control circuit scheduling the store-from-buffer command and sending the store command to the memory devices over a fourth communications link, and sending the store-from-buffer command along with the store data tag to the data buffer circuit over the third communications link.

20. The method of claim 19 , further comprising the data buffer circuit, in response to receiving the store-from-buffer command, sending the incoming data from the data buffer circuit to the memory devices.

Assignees

• IBM

Inventors

• Carlough Steven R
• Eickhoff Susan M
• Maule Warren E
• Meaney Patrick J
• Powell Stephen J
• Van Huben Gary A
• Zheng Jie

Classifications

• G11C7/109 Primary

  Control signal input circuits · CPC title

• G06F3/0626

  Reducing size or complexity of storage systems · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title