Host controlled data chip address sequencing for a distributed memory buffer system

Patent metadata

Field	Value
Publication number	US-10747442-B2
Application number	US-201715825867-A
Country	US
Kind code	B2
Filing date	Nov 29, 2017
Priority date	Nov 29, 2017
Publication date	Aug 18, 2020
Grant date	Aug 18, 2020

Abstract

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.

First claim

What is claimed is:

1. A memory system for storing data in at least one memory device in response to commands received from a Host, the memory system comprising:
a memory control circuit to receive commands from the Host and to output module command and control signals;
the at least one memory device configured to store incoming data and receive command signals from the memory control circuit;
at least one data buffer circuit associated with the at least one memory device;
a data communications link for communicating data between the Host and the at least one memory device, wherein the data communications link includes a data buffer data communications link connected directly to the at least one data buffer circuit for receiving data from the Host, and a data transfer link connected directly to the at least one data buffer circuit and connected directly to the at least one memory device;
a memory control circuit control communications link connected directly to the memory control circuit for receiving commands from the Host;
a memory device control communications link to send commands and address locations to the at least one memory device, the memory device control communications link connected directly to the memory control circuit and directly to the at least one memory device; and
a data buffer control communications link for notifying the at least one data buffer circuit when to execute scheduled operations, the data buffer control communications link connected directly to the memory control circuit and connected directly to the at least one data buffer circuit,
wherein the system further comprises at least one module having the memory control circuit formed on a single chip and arranged on the module, a group of the data buffer circuits formed on separate chips and arranged on the module, and a plurality of memory devices formed on separate chips and arranged in groups on the module, and
wherein the at least one data buffer circuit is configured to:

receive incoming data and a next to be used Host store data tag from the Host wherein a Host store data tag specifies a data buffer location in the at least one data buffer circuit; and
after receiving the next to be used Host store data tag from the Host, automatically move incoming data received from the Host into the data buffer location in the at least one data buffer circuit identified by the previously received next to be used Host store data tag.

2. The system of claim 1 , wherein the next to be used Host store data tag receivable from the Host by the at least one data buffer circuit is configured to be sent over the data buffer data communication link.

3. The system of claim 2 , wherein the system is configured to move incoming data into the at least one data buffer circuit after a configuration delay.

4. The system of claim 3 , wherein the memory control circuit is configured to:
receive a Host store command and the next to be used Host store data tag from the Host;
in response to receiving the Host store command, decode the Host store command into a write-to-buffer command and store-from-buffer command; and
send the write-to-buffer command and no Host store data tag to the data buffer circuit over the data buffer control communications link.

5. The system of claim 4 , wherein the system is configured to receive the next to be used Host store data tag from the Host by the at least one data buffer circuit before the at least one data buffer circuit receives the write-to-buffer command from the memory control circuit.

6. The system of claim 5 , wherein the memory control circuit is configured to schedule the store-from-buffer command and send a memory device store command to the at least one memory device, the memory device store command comprising a command and an address location to store the incoming data in the at least one memory device.

7. The system of claim 5 , wherein the memory control circuit is further configured to send the store-from-buffer command along with the next to be used Host store data tag to the at least one data buffer circuit.

8. The system of claim 7 , wherein the system is configured to send the store-from-buffer command and the next to be used Host store data tag to the at least one data buffer circuit over the data buffer data control communication link between the memory control circuit and the data buffer circuit.

9. The system of claim 7 , wherein the data buffer circuit is further configured to pull the incoming data from the data buffer location identified by the next to be used Host store data tag received from the memory control circuit over the data buffer data control communications link and send the incoming data to the at least one memory device.

10. A memory system for reading and writing data from a Host to at least one memory device, the system comprising:
at least one module having at least one memory control circuit formed on a single chip and arranged on the module, a group of data buffer circuits formed on separate chips and arranged on the module, and a plurality of memory devices formed on separate chips and arranged in groups on the module;
the at least one memory control circuit to receive commands from the Host and to output command and control signals;
each memory device configured to read and store data, and receive command signals from the memory control circuit;
each data buffer circuit associated with at least one of the plurality of memory control circuits;
a data communications link for communicating data between the Host and the at least one memory device, wherein the data communications link includes a data buffer data communications link connected directly to each of the group of data buffer circuits for receiving data from the Host, and a data transfer link connected directly to each data buffer circuit and connected directly to at least one of the plurality of memory devices; and
a control communications link for transmitting memory operation signals of the memory system, wherein the control communications link includes a memory device control communications link directly connected to the at least one memory control circuit and directly to each of the memory devices, a data buffer control communications link connected directly to the at least one memory control circuit and connected directly to each of the group of data buffer circuits, and a memory control circuit communications link directly connected to the at least one memory control circuit for receiving commands from a Host;
wherein the at least one data buffer circuit is configured to:

receive a next to be used Host store data tag from the Host;
after receiving the next to be used Host store data tag from the Host, receive incoming store data from the Host over the data buffer data communications link; and
in response to receiving a write-to-buffer command send the incoming store data into a local data buffer circuit identified by the next to be used Host store data tag received from the Host, and
wherein the at least one memory control circuit is configured to:

receive a store command along with the next to be used Host store data tag from the Host;
decode the store command into the write-to-buffer command and a store-from-buffer command; and
send the write-to-buffer command to at least one data buffer circuit.

11. The system of claim 10 , wherein the system is configured so that the next to be used Host store data tag associated with the write-to-buffer command and sent to the at least one data buffer circuit is not sent over the data buffer data communications link between the memory control circuit and the at least one data buffer circuit.

12. The system of claim 10

Assignees

• IBM

Inventors

• Carlough Steven R
• Eickhoff Susan M
• Maule Warren E
• Meaney Patrick J
• Powell Stephen J
• Van Huben Gary A
• Zheng Jie

Classifications

• G06F13/1673 Primary

  using buffers · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F2212/205

  Hybrid memory, e.g. using both volatile and non-volatile memory · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title