Common high and low random bit error correction logic

Patent metadata

Field	Value
Publication number	US-10824504-B2
Application number	US-201815953805-A
Country	US
Kind code	B2
Filing date	Apr 16, 2018
Priority date	Apr 16, 2018
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. Each of the memory devices are characterized as one of a high random bit error rate (RBER) and a low RBER memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices. The memory buffer device also includes common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The common error correction logic includes a plurality of error correction units which provide different complexity levels of error correction and have different latencies. The error correction units include a first fast path error correction unit for isolating and correcting random symbol errors.

First claim

What is claimed is:

1. A memory system comprising:
a memory module comprising:
a plurality of memory devices, each of the plurality of memory devices characterized as one of a high random bit error rate (RBER) memory device and a low RBER memory device; and
a memory buffer device comprising:
a read data interface configured to receive data read from a memory address corresponding to a location on one of the plurality of memory devices; and
common error correction logic configured to detect and correct error conditions in data read from both high RBER memory devices and low RBER memory devices, the common error correction logic comprising:
a plurality of error correction units which provide different complexity levels of error correction and have different latencies, the plurality of error correction units comprising a first fast path error correction unit for isolating and correcting random symbol errors, a latency of the first fast path error correction unit less than a latency of an other of the plurality of error correction units,

wherein the plurality of error correction units further comprise a second fast path error correction unit configured for isolating and correcting a failing memory device of the plurality of memory devices along with random symbol errors, a latency of the second fast path error correction unit higher than the latency of the first fast path error correction unit, and
wherein a spare memory device is varied in to replace the failing memory device.

2. The memory system of claim 1 , wherein the common error correction logic further comprises:
a bypass path for transmitting data received at the read data interface directly to a requestor of the data, the bypass path having a bypass latency less than the latency of the first fast path error correction unit.

3. The memory system of claim 1 , wherein the second fast path error correction unit is further configured for isolating and correcting for two failing memory devices.

4. The memory system of claim 1 , wherein the common error correction logic further comprises read re-try logic configured to request read data from an other memory address to isolate a failing memory device by eliminating at least one random symbol error.

5. The memory system of claim 1 , wherein the received data comprises one-hundred and twenty-eight data symbols and twenty-two error correction code (ECC) symbols, and the first fast path error correction unit isolates and corrects random symbol errors in up to two of the one-hundred and twenty-eight data symbols and twenty-two ECC symbols.

6. The memory system of claim 5 , wherein the second fast path error correction unit is configured to isolate and correct the failing memory device and a random symbol error in up to four data symbols, and a latency of the second fast path error correction unit is longer than the latency of the first fast path error correction unit.

7. The memory system of claim 6 , wherein the plurality of correction units further comprise a third error correction unit configured to isolate and correct a failing memory device and random symbol errors in up to nine data symbols, a latency of the third fast path error correction unit longer than the latency of the second fast path error correction unit.

8. The memory system of claim 1 , wherein the common error correction logic further comprises a syndrome discrepancy calculator configured to determine whether additional errors are present at different stages of error correction.

9. A memory buffer device comprising:
a read data interface configured to receive data read from a memory address corresponding to a location on one of a plurality of memory devices, each of the plurality of memory devices characterized as one of a high random bit error rate (RBER) memory device and a low RBER memory device; and
common error correction logic configured to detect and correct error conditions in data read from both high RBER memory devices and low RBER memory devices, the common error correction logic comprising:
a plurality of error correction units which provide different complexity levels of error correction and have different latencies, the plurality of error correction units comprising a first fast path error correction unit for isolating and correcting random symbol errors, a latency of the first fast path error correction unit less than a latency of an other of the plurality of error correction units,
wherein the plurality of error correction units further comprise a second fast path error correction unit configured for isolating and correcting a failing memory device of the plurality of memory devices along with random symbol errors, a latency of the second fast path error correction unit higher than the latency of the first fast path error correction unit, and
wherein a spare memory device is varied in to replace the failing memory device.

10. The memory buffer device of claim 8 , wherein the common error correction logic further comprises:
a bypass path for transmitting data received at the read data interface directly to a requestor of the data, the bypass path having a bypass latency less than the latency of the first fast path error correction unit.

11. The memory buffer device of claim 9 , wherein the second fast path error correction unit is further configured for isolating and correcting for two failing memory devices.

12. The memory buffer device of claim 9 , wherein the common error correction logic further comprises read re-try logic configured to request read data from an other memory address to isolate a failing memory device by eliminating at least one random symbol error.

13. The memory buffer device of claim 9 , wherein the received data comprises one-hundred and twenty-eight data symbols and twenty-two error correction code (ECC) symbols, and the first fast path error correction unit isolates and corrects random symbol errors in up to two of the one-hundred and twenty-eight data symbols and twenty-two ECC symbols.

14. The memory buffer device of claim 13 , wherein the plurality of correction units further comprise a third error correction unit configured to isolate and correct a failing memory device and random symbol errors in up to nine data symbols, the second fast path error correction unit is configured to correct the failing memory device and a random symbol error in up to four data symbols, and a latency of the second fast path error correction unit is longer than the latency of the first fast path error correction unit and less than a latency of the third error correction unit.

15. A method comprising:
receiving data read from a memory address corresponding to a location on one of a plurality of memory devices located coupled to a memory module, each of the plurality of memory devices characterized as one of a high random bit error rate (RBER) memory device and a low RBER memory device;
executing common error correction logic using the received data as input to generate corrected data, the common error correction logic configured to detect and correct error conditions in both high random symbol error rate (RBER) memory devices and low RBER memory devices, the common error correction logic comprising a plurality of error correction units which provide different complexity levels of error correction and have different latencies, the plurality of error correction units comprising a first fast path error correction unit for isolating and correcting random symbol errors, a latency of the first fast path error correction unit less than a latency of an other of the plurality of error correction units; and
outputting the corrected

Assignees

• IBM

Inventors

• O'Connor Jr James A
• Trager Barry M
• Maule Warren E
• Gollub Marc A
• Michael Brad W
• Meaney Patrick J

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title