Autonomous dram scrub and error counting

Patent metadata

Field	Value
Publication number	US-10628248-B2
Application number	US-201615070273-A
Country	US
Kind code	B2
Filing date	Mar 15, 2016
Priority date	Mar 15, 2016
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.

First claim

The invention claimed is:

1. A method of dynamic random access memory (DRAM) scrub and error counting in a memory of a computer system, the method comprising:
performing autonomous scrub operations at memory locations in a DRAM based on a timing of refresh operations at the DRAM, the DRAM comprising a memory array, and one or more registers for storing an internal address pointer, an error count, and an error threshold, the performing including repeating a cycle that includes a scrub operation and a refresh operation until a read/modify/write (RMW) operation has been performed at each of the memory locations in the memory array, the cycle comprising:
receiving an indication that a refresh command has been registered at the DRAM;
triggering execution of the RMW operation based on receiving the indication that a refresh command has been registered at the DRAM;
based on the triggering, executing the RMW operation at a memory location in the memory array indicated by the internal address pointer, the executing including writing corrected bits to the memory location;
incrementing the error count in response to detecting an error during the executing; and
incrementing the internal address pointer to indicate a next memory location in the memory array;

comparing the error count to the error threshold, wherein the error threshold indicates a number of errors in excess of an expected number of errors, the expected number of errors set by a manufacturer of the DRAM and not visible to purchasers or users of the DRAM; and
initiating an alert in response to the error count exceeding the error threshold.

2. The method of claim 1 , wherein the performing is independent of a memory controller.

3. The method of claim 1 , wherein the comparing and the initiating are in response to a request from a memory controller.

4. The method of claim 1 , wherein the refresh command is registered by a memory controller.

5. The method of claim 1 , wherein the DRAM is in a self-refresh mode and the refresh command is registered by the DRAM.

6. The method of claim 1 , further comprising:
resetting the error count to zero subsequent to the comparing; and
repeating the performing and comparing.

7. The method of claim 1 , wherein the alert is sent to a memory controller via a dedicated pin on the DRAM, and the alert includes the number of errors in excess of an expected number of errors.

8. The method of claim 1 further comprising:
resetting the error count to zero subsequent to the comparing; and
repeating the performing and comparing, wherein
the DRAM is in a self-refresh mode,
the refresh command is registered by the DRAM.,
the alert includes the number of errors in excess of an expected number of errors, and
the alert is sent to a memory controller via a dedicated pin on the DRAM, and the method further comprises.

9. A memory system comprising:
a memory device, the memory device including a dynamic random access memory (DRAM), the DRAM comprising a memory array, and one or more registers for storing an internal address pointer, an error count, and an error threshold, the memory device configured for:
performing autonomous scrub operations at memory locations in the DRAM based on a timing of refresh operations at the DRAM, the performing including repeating a cycle that includes a scrub operation and a refresh operation until a read/modify/write (RMW) operation has been performed at each of the memory locations in the memory array, the cycle comprising:
receiving an indication that a refresh command has been registered at the DRAM;
triggering execution of the RMW operation based on receiving the indication that a refresh command has been registered at the DRAM;
based on the triggering, executing the RMW operation at a memory location in the memory array indicated by the internal address pointer, the executing including writing corrected bits to the memory location;
incrementing the error count in response to detecting an error during the executing; and
incrementing the internal address pointer to indicate a next memory location in the memory array;

comparing the error count to an error threshold, wherein the error threshold indicates a number of errors in excess of an expected number of errors, the expected number of errors set by a manufacturer of the DRAM and not visible to purchasers or users of the DRAM; and
initiating an alert in response to the error count exceeding the error threshold.

10. The memory system of claim 9 , wherein the performing is independent of a memory controller.

11. The memory system of claim 9 , wherein the comparing and the initiating are in response to a request from a memory controller.

12. The memory system of claim 9 , wherein the refresh command is registered by a memory controller.

13. The memory system of claim 9 , wherein the DRAM is in a self-refresh mode and the refresh command is registered by the DRAM.

14. The memory system of claim 9 , wherein the memory device is further configured for:
resetting the error count to zero subsequent to the comparing; and
repeating the performing and comparing.

15. The memory system of claim 9 , wherein the alert is sent to a memory controller via a dedicated pin on the DRAM, and the alert includes the number of errors in excess of an expected number of errors.

16. The memory system of claim 9 , wherein the memory device is further configured for:
resetting the error count to zero subsequent to the comparing; and
repeating the performing and comparing, wherein
the DRAM is in a self-refresh mode,
the refresh command is registered by the DRAM.,
the alert includes the number of errors in excess of an expected number of errors, and
the alert is sent to a memory controller via a dedicated pin on the DRAM, and the method further comprises.

17. A computer program product for dynamic random access memory (DRAM) scrub and error counting in a memory of a computer system, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing circuitry to cause the processing circuitry to:
perform autonomous scrub operations at memory locations in the DRAM based on timing of refresh operations at the DRAM, the DRAM comprising a memory array, and one or more registers for storing an internal address pointer, an error count, and an error threshold, the performing including repeating a cycle that includes a scrub operation and a refresh operation until a read/modify/write (RMW) operation has been performed at each of the memory locations in the memory array, the cycle comprising:
receiving an indication that a refresh command has been registered at the DRAM;
triggering an execution of the RMW operation based on receiving the indication that a refresh command has been registered at the DRAM;
based on the triggering, executing the RMW operation at a memory location in the memory array indicated by the internal address pointer, the executing including writing corrected bits to the memory location;
incrementing the error count in response to detecting an error during the executing; and
incrementing the internal address pointer to indicate a next memory location in the memory array;

compare the error count to an error threshold, wherein the error threshold indicates a number of errors in excess of an expected number of errors, the expected number of errors set by a manufacturer of the DRAM and not visible to purchasers or users of the DRAM; and
initiate an alert in response to the error count exce

Assignees

• IBM

Inventors

• Chinnakkonda Vidyapoornachary Diyanesh B
• Gollub Marc A
• Maule Warren E
• Sawan Tony E

Classifications

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/076 Primary

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title