Memory mirror invocation upon detecting a correctable error

Patent metadata

Field	Value
Publication number	US-10613951-B2
Application number	US-201715702787-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Sep 13, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

Aspects of the invention include fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory. An error status of the data fetched from the primary memory is determined. The error status is one of correctable error (CE), uncorrectable error (UE), and no error. Based at least in part on determining that the data fetched from the primary memory has the error status of no error, the data fetched from the primary memory is output to the requestor. Based at least in part on determining that the data fetched from the primary memory has the error status of UE or CE, the data requested by the requestor is fetched from the secondary memory.

First claim

What is claimed is:

1. A computer-implemented method comprising:
fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory;
determining an error status of the data fetched from the primary memory, the error status selected from the group consisting of correctable error (CE), uncorrectable error (UE), and no error;
based at least in part on determining that the data fetched from the primary memory has the error status of no error, outputting the data fetched from the primary memory to the requestor;
based at least in part on determining that the data fetched from the primary memory has the error status of UE, fetching the data requested by the requestor from the secondary memory;
based at least in part on determining that the data fetched from the primary memory has the error status of CE, fetching the data requested by the requestor from the secondary memory;
based at least in part on fetching the data requested by the requestor from the secondary memory, determining the error status of the data fetched from the secondary memory;
based at least in part on determining that the data fetched from the secondary memory has the error status of no error, outputting the data fetched from the secondary memory to the requestor;
based at least in part on detecting that both the data fetched from the primary memory and the data fetched from the secondary memory have the error status of UE:
setting a UE flag to indicate a UE; and
outputting the UE flag to the requestor; and

based at least in part on detecting that both the data fetched from the primary memory and the data fetched from the secondary memory have the error status of CE:
comparing contents of the data fetched from the primary memory and the data fetched from the secondary memory;
outputting the data fetched from the primary memory to the requestor based at least in part on contents of the data fetched from the primary memory and contents of the data fetched from the secondary memory having the same value; and
setting the UE flag to indicate a UE and outputting the UE flag to the requestor based at least in part on contents of the data fetched from the primary memory and contents of the data fetched from the secondary memory having a different value.

2. The computer-implemented method of claim 1 , further comprising:
based at least in part on determining that the data fetched from the primary memory has the error status of CE and that the data fetched from the secondary memory has the error status of UE, outputting the data fetched from the primary memory to the requestor; and
based at least in part on determining that the data fetched from the primary memory has the error status of UE and that the data fetched from the secondary memory has the error status of CE, outputting the data fetched from the secondary memory to the requester.

3. The computer-implemented method of claim 1 , further comprising:
based at least in part on detecting that the data fetched from the secondary memory has the error status of CE, outputting an UE indicator to the requestor.

4. The computer-implemented method of claim 1 , wherein the primary memory and the secondary memory each include a memory device.

5. The computer-implemented method of claim 1 , wherein the primary memory and the secondary memory each include a memory module comprising one or more memory devices.

6. A system comprising:
a memory having computer readable instructions; and
one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory;
determining an error status of the data fetched from the primary memory, the error status selected from the group consisting of correctable error (CE), uncorrectable error (UE), and no error;
based at least in part on determining that the data fetched from the primary memory has the error status of no error, outputting the data fetched from the primary memory to the requestor;
based at least in part on determining that the data fetched from the primary memory has the error status of UE, fetching the data requested by the requestor from the secondary memory;
based at least in part on determining that the data fetched from the primary memory has the error status of CE, fetching the data requested by the requestor from the secondary memory;
based at least in part on fetching the data requested by the requestor from the secondary memory, determining the error status of the data fetched from the secondary memory;
based at least in part on determining that the data fetched from the secondary memory has the error status of no error, outputting the data fetched from the secondary memory to the requestor;
based at least in part on detecting that both the data fetched from the primary memory and the data fetched from the secondary memory have the error status of UE:
setting a UE flag to indicate a UE; and
outputting the UE flag to the requestor; and
based at least in part on detecting that both the data fetched from the primary memory and the data fetched from the secondary memory have the error status of CE:
comparing contents of the data fetched from the primary memory and the data fetched from the secondary memory;
outputting the data fetched from the primary memory to the requestor based at least in part on contents of the data fetched from the primary memory and contents of the data fetched from the secondary memory having the same value; and
setting the UE flag to indicate a UE and outputting the UE flag to the requestor based at least in part on contents of the data fetched from the primary memory and contents of the data fetched from the secondary memory having a different value.

7. The system of claim 6 , the operations further comprising:
based at least in part on determining that the data fetched from the primary memory has the error status of CE and that the data fetched from the secondary memory has the error status of UE, outputting the data fetched from the primary memory to the requestor; and
based at least in part on determining that the data fetched from the primary memory has the error status of UE and that the data fetched from the secondary memory has the error status of CE, outputting the data fetched from the secondary memory to the requester.

8. The system of claim 6 , the operations further comprising:
based at least in part on detecting that the data fetched from the secondary memory has the error status of CE, outputting an UE indicator to the requestor.

9. The system of claim 6 , wherein the primary memory and the secondary memory each include a memory device.

10. The system of claim 6 , wherein the primary memory and the secondary memory each include a memory module comprising one or more memory devices.

11. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
fetching data requested by a requestor from a primary memory in a memory system that includes the primary memory and a secondary memory mirroring the primary memory;
determining an error status of the data fetched from the primary memory, the error status selected from the group consisting of correctable error (CE), uncorrectable error (UE), and no error;
based at least in part on deter

Assignees

• IBM

Inventors

• Gollub Marc A
• Maule Warren E
• Meaney Patrick J

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/2087 Primary

  with a common controller · CPC title

• G06F11/1666 Primary

  where the redundant component is memory or memory area · CPC title

• G06F11/167

  Error detection by comparing the memory output · CPC title

• G06F11/2069

  Management of state, configuration or failover · CPC title