Redundant voltage regulator for memory devices

Patent metadata

Field	Value
Publication number	US-11264077-B2
Application number	US-202117150514-A
Country	US
Kind code	B2
Filing date	Jan 15, 2021
Priority date	Dec 15, 2017
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

First claim

What is claimed is:

1. A system comprising:
at least one memory module having a circuit, the at least one memory module including a plurality of dynamic random access memory devices having a circuit mounted on the module, and a first voltage regulator having a circuit mounted on the module, the first voltage regulator configured to supply at least one of a plurality of voltage levels to a plurality of voltage domains on the memory module for supplying voltage to the plurality of memory devices, and
a system board including a second voltage regulator having a circuit configured to supply voltage to the first voltage regulator, and a third redundant voltage regulator, the third redundant voltage regulator having a circuit configured to supply at least one of the plurality of voltage levels to the plurality of voltage domains on the memory module, wherein the at least one of the plurality of voltage levels supplied by the third redundant voltage regulator is the same voltage level as the at least one voltage level supplied by the first voltage regulator,
wherein the memory devices are configured to be accessed in reduced bandwidth frequency to secure the memory content of the memory devices in response to an event.

2. The system of claim 1 , wherein the third redundant voltage regulator supplies the plurality of voltage levels to the voltage domains on the at least one memory module through a plurality of blade pins.

3. The system of claim 1 , wherein the third redundant voltage regulator is configured to continue to supply voltage to the plurality of voltage domains on the memory module in the event that the first voltage regulator fails.

4. The system of claim 1 , wherein the third voltage regulator is configured to supply the at least one of a plurality of voltage levels to the plurality of voltage domains in parallel to the at least one of the plurality of voltage levels supplied by the first voltage regulator.

5. The system of claim 1 , wherein the memory module is configured to send a signal to the system board in response to a first voltage regulator failure or an impending first voltage regulator failure.

6. The system of claim 5 , wherein the signal sent to the system board upon the failure of or the impending failure of the first voltage regulator can be received from at least one of a RCD device mounted on the module, a special RFU pin on the module, or both.

7. The system of claim 1 , wherein the system is configured so that a power-up sequence of the third voltage regulator occurs after a power-up sequence of the first voltage regulator has completed.

8. The system of claim 1 , wherein the third redundant voltage regulator improves the signal integrity of the memory devices by improving voltage tolerance of at least one voltage domain on the memory module.

9. The system of claim 1 , wherein the third redundant voltage regulator is configured to supply at least one of a plurality of voltage levels to a plurality of memory modules.

10. A memory subsystem comprising:
at least one memory module having a substrate to which a voltage regulator and a plurality of memory chips having one or more circuits is mounted, the voltage regulator having a circuit configured to supply a power supply signal from a system power supply and to output two or more power signals, each power signal providing a different, regulated voltage level, which regulated voltage levels are each configured to be routed to each of the plurality of memory chips; and
a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals providing external different, regulated voltage levels which are the same voltage levels as the voltage levels output by the voltage regulator mounted on the memory module,
wherein the redundant voltage regulator is configured to be always actively on and supplying at least one of the two or more power signals to the memory module; and
wherein the at least one memory module is configured and adapted so that the plurality of voltage levels supplied by the redundant voltage regulator are parallel to the two or more power signals output by the memory voltage regulator.

11. The memory subsystem of claim 10 , wherein the redundant voltage regulator is configured to output two or more power signals of different regulated voltage levels to a plurality of memory modules.

12. A system comprising:
at least one memory module having a circuit, the at least one memory module including a plurality of dynamic random access memory devices having a circuit mounted on the at least one memory module, and a first voltage regulator having a circuit mounted on the at least one memory module, the first voltage regulator configured to supply at least one of a plurality of voltage levels to a plurality of voltage domains on the at least one memory module for supplying voltage to the plurality of memory devices, and
a system board separate from the at least one memory module including a second voltage regulator and a third redundant voltage regulator, the second voltage regulator having a circuit configured to supply voltage to the first voltage regulator, and the third redundant voltage regulator having a circuit configured to supply at least one of the plurality of voltage levels directly to the plurality of voltage domains on the at least one memory module, wherein the at least one of the plurality of voltage levels supplied by the third redundant voltage regulator is the same voltage level as the at least one voltage level supplied by the first voltage regulator.

13. The system of claim 12 , wherein the third redundant voltage regulator supplies the plurality of voltage levels to the voltage domains on the at least one memory module through a plurality of blade pins.

14. The system of claim 12 , wherein the third redundant voltage regulator is configured to continue to supply voltage to the plurality of voltage domains on the at least one memory module in the event that the first voltage regulator fails.

15. The system of claim 12 , wherein the third voltage regulator is configured to supply the at least one of a plurality of voltage levels to the plurality of voltage domains in parallel to the at least one of the plurality of voltage levels supplied by the first voltage regulator.

16. The system of claim 12 , wherein the at least one memory module is configured to send a signal to the system board in response to a first voltage regulator failure or an impending first voltage regulator failure.

17. The system of claim 16 , wherein the signal sent to the system board upon the failure of or the impending failure of the first voltage regulator can be received from at least one of a RCD device mounted on the at least one memory module, a special RFU pin on the at least one module, or both.

18. The system of claim 12 , wherein the system is configured so that a power-up sequence of the third voltage regulator occurs after a power-up sequence of the first voltage regulator has completed.

19. The system of claim 12 , wherein the third redundant voltage regulator improves the signal integrity of the memory devices by improving voltage tolerance of at least one voltage domain on the at least one memory module.

20. The system of claim 12 , wherein the third redundant voltage regulator is configured to supply at least one of a plurality of voltage levels to a plurality of memory modules.

Assignees

• IBM

Inventors

• Connolly Brian J
• Kim Kyu-Hyoun
• Maule Warren E

Classifications

• G11C29/702

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title