Method for forming dynamic random access memory structure
US-10763264-B2 · Sep 1, 2020 · US
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Lee Sho-Shen patents
Lee Sho-Shen is listed as an inventor on 22 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Lee Sho-Shen |
| Total patents | 22 |
| First publication | Feb 10, 2015 |
| Latest publication | Sep 1, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Method of forming layout of semiconductor device
US-10707213-B2 · Jul 7, 2020 · US
Manufacturing method for semiconductor pattern
US-10707092-B1 · Jul 7, 2020 · US
Manufacturing method for semiconductor pattern
US-2020203176-A1 · Jun 25, 2020 · US
Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
US-10692785-B2 · Jun 23, 2020 · US
Method of forming layout of semiconductor device
US-2020111791-A1 · Apr 9, 2020 · US
Method of forming overlay mark structure
US-2020013724-A1 · Jan 9, 2020 · US
Method for forming dynamic random access memory structure
US-2020013783-A1 · Jan 9, 2020 · US
Method of forming overlay mark structure
US-10529667-B1 · Jan 7, 2020 · US
Dynamic random access memory structure and method for forming the same
US-10453849-B2 · Oct 22, 2019 · US
Recent patents
Latest publications not already listed above.
Dynamic random access memory structure and method for forming the same
US-2019273083-A1 · Sep 5, 2019 · US
Method for monitoring semiconductor process
US-10373915-B1 · Aug 6, 2019 · US
Method for manufacturing semiconductor device
US-10276395-B2 · Apr 30, 2019 · US
Measurement mark and method for monitoring semiconductor process
US-10177094-B1 · Jan 8, 2019 · US
Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
US-2018374765-A1 · Dec 27, 2018 · US
Method for manufacturing semiconductor device
US-2018286692-A1 · Oct 4, 2018 · US
Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
US-10079185-B1 · Sep 18, 2018 · US
Overlay marks and semiconductor process using the overlay marks
US-9490217-B1 · Nov 8, 2016 · US
Overlay marks and semiconductor process using the overlay marks
US-2016307850-A1 · Oct 20, 2016 · US
Photomask and fabrication method thereof
US-9304389-B2 · Apr 5, 2016 · US
Photomask and fabrication method thereof
US-2015118602-A1 · Apr 30, 2015 · US
Calculation method for generating layout pattern in photomask
US-8954919-B1 · Feb 10, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| United Microelectronics Corp | 22 |
| Fujian Jinhua Integrated Circuit Co Ltd | 15 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H01L23/544 | 7 |
| H01L2223/54426 | 7 |
| H10P50/73 | 6 |
| H01L21/31144 | 6 |
| H10W46/301 | 6 |