Overlay marks and semiconductor process using the overlay marks

Patent metadata

Field	Value
Publication number	US-9490217-B1
Application number	US-201514687912-A
Country	US
Kind code	B1
Filing date	Apr 15, 2015
Priority date	Apr 15, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

First claim

What is claimed is:

1. An overlay mark, formed along with two successive layers above a substrate, wherein both said substrate and said overlay mark comprise at least two pattern zones having periodic structures with different orientations, and said periodic structures of said overlay mark formed along with at least one of said two successive layers are orthogonally overlapped with said periodic structures of said substrate.

2. The overlay mark of claim 1 , wherein said periodic structures of said overlay mark formed along with said two successive layers are both orthogonally overlapped with said periodic structures of said substrate.

3. The overlay mark of claim 1 , wherein said periodic structures of said substrate in different pattern zones have different pitches.

4. The overlay mark of claim 1 , wherein said periodic structures formed along with one of said two successive layers is juxtaposed with said periodic structures formed along with the other one of said two successive layers with the same orientation.

5. The overlay mark of claim 1 , wherein said two successive layers are a gate layer and contact photoresist.

6. The overlay mark of claim 1 , wherein said two successive layers are a gate layer and an inter-layer dielectric.

7. The overlay mark of claim 1 , wherein said periodic structure of said substrate is fins, mandrels or trenches.

8. The overlay mark of claim 1 , wherein said periodic structure in said two successive layers is a parallel alignment bar.

9. The overlay mark of claim 1 , wherein said periodic structures of said overlay mark formed along with said two successive layers are on different level.

10. An overlay mark, formed along with two successive layers above a substrate, wherein both said substrate and said overlay mark comprise only one pattern zone having periodic structures, and said periodic structures of said overlay mark formed along with at least one of said two successive layers are orthogonally overlapped with said periodic structures of said substrate.

11. The overlay mark of claim 10 , wherein said periodic structures of said overlay mark formed along with said two successive layers are both orthogonally overlapped with said periodic structures of said substrate.

12. The overlay mark of claim 10 , wherein said periodic structures formed along with one of said two successive layers is juxtaposed with said periodic structures formed along with the other one of said two successive layers with the same orientation.

13. The overlay mark of claim 10 , wherein said two successive layers are a gate layer and contact photoresist.

14. The overlay mark of claim 10 , wherein said two successive layers are a gate layer and an inter-layer dielectric.

15. The overlay mark of claim 10 , wherein said periodic structure of said substrate is fins, mandrels or trenches.

16. The overlay mark of claim 10 , wherein said periodic structure in said two successive layers is a parallel alignment bar.

17. The overlay mark of claim 10 , wherein said periodic structures of said overlay mark formed along with said two successive layers are on different level.

18. A semiconductor process of forming overlay marks, comprising:
patterning a substrate to form periodic structures in at least two pattern zones, wherein said periodic structures in different said pattern zones have different orientations; and
forming two successive layers with respective overlay marks above said substrate, wherein both said overlay marks have at least two said pattern zones, wherein said pattern zone has periodic structures with different orientations, and said periodic structures of said two successive layers are orthogonally overlapped with said periodic structures of said substrate.

19. The semiconductor process of forming overlay marks of claim 18 , wherein said periodic structures in one of said two successive layers is juxtaposed with said periodic structures with the same orientation in the other one of said two successive layers.

20. The semiconductor process of forming overlay marks of claim 18 , wherein said periodic structures with different orientations have different pitches.

Assignees

• United Microelectronics Corp

Inventors

• Lin Chia-Ching
• Liou En-Chiuan
• Wang Chia-Hung
• Lee Sho-Shen

Classifications

• G03F7/70683

  Mark designs · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H01L2223/5442

  Electricity · mapped topic

• H01L2223/54426

  Electricity · mapped topic