Manufacturing method for semiconductor pattern

Patent metadata

Field	Value
Publication number	US-10707092-B1
Application number	US-201916245163-A
Country	US
Kind code	B1
Filing date	Jan 10, 2019
Priority date	Dec 19, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

First claim

What is claimed is:

1. A method of fabricating a semiconductor pattern, comprising:
providing a substrate, having an oxide layer disposed thereon and a first material layer on the oxide layer, wherein a first region and a second region are defined on the substrate;
performing a first etching step, to remove a portion of the first material layer in the first region;
forming a plurality of first patterns on the first material layer in the first region, wherein the first pattern is formed by a first sidewall image transfer (SIT) step;
forming a second composite layer on the first pattern;
forming a second pattern layer on the second composite layer in the first region; and
performing a second etching step, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.

2. The method of claim 1 , wherein after the first etching step is performed, the first material layer has a stepped cross section, and a top surface in the first region is lower than a top surface in the second region.

3. The method of claim 1 , wherein the first material layer comprises an advanced pattern film (APF).

4. The method of claim 1 , wherein the first sidewall image transfer (SIT) step comprising:
forming a first composite layer and a first sacrificial pattern layer on the first material layer;
forming a first spacer material layer on the first sacrificial pattern layer;
performing a third etching step to remove a portion of the first spacer material layer;
removing the first sacrificial pattern layer completely; and
using the remaining first spacer material layer as a mask, to etch a portion of the first composite layer.

5. The method of claim 1 , wherein the second pattern is formed by an another sidewall image transfer (SIT) step.

6. The method of claim 5 , wherein the another sidewall image transfer (SIT) step comprising:
forming a second composite layer and a second sacrificial pattern layer on the first material layer;
forming a second spacer material layer on the second sacrificial pattern layer;
performing a fourth etching step to remove a portion of the second spacer material layer;
removing the second sacrificial pattern layer completely; and
using the remaining second spacer material layer as a mask, to etch a portion of the second composite layer.

7. The method of claim 1 , wherein after the oxide layer is etched, a plurality of the storage node contact holes are formed.

8. The method of claim 1 , wherein the first pattern is only located within the first region.

9. The method of claim 1 , wherein the second pattern is only located within the first region.

10. The method of claim 4 , wherein the first composite layer comprises a silicon oxynitride layer, an organic dielectric layer (organic dielectric layer, ODL) and a silicon oxynitride layer.

11. The method of claim 1 , wherein the second composite layer comprises a silicon oxynitride layer, an organic dielectric layer (organic dielectric layer, ODL) and a silicon oxynitride layer.

12. The method of claim 1 , wherein the first pattern comprises a plurality of parallel strip structures, arranged along a first direction and parallel to each other.

13. The method of claim 12 , wherein the second pattern comprises a plurality of parallel strip structures, arranged along a second direction and parallel to each other, and wherein the second direction is not parallel to the first direction.

14. The method of claim 1 , wherein the semiconductor pattern is used as a storage node contact hole in a semiconductor structure.

15. The method of claim 1 , wherein a portion of the first pattern and a portion of the second pattern are located above the first material layer.

Assignees

• United Microelectronics Corp

Inventors

• Wang Chia-Hung
• Liou En-Chiuan
• Chen Chien-Hao
• Lee Jhao-Hao
• Lee Sho-Shen
• Chiang Chih-Yu

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/041

  the barrier, adhesion or liner layers being discontinuous · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title