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Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
US2018374765A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018374765-A1 |
| Application number | US-201816057826-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 8, 2018 |
| Priority date | Jun 23, 2017 |
| Publication date | Dec 27, 2018 |
| Grant date | — |
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Abstract
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A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped pattern and the second pattern are composed of a plurality of spacer patterns spaced apart from each other.
First claim
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What is claimed is: 1 . A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage, comprising: a first inverted-T shaped pattern with a base portion extending in a first direction and a middle portion extending from said base portion in a second direction orthogonal to said first direction; and a second pattern adjacent and spaced apart from said base portion of said first inverted-T shaped pattern, wherein said first inverted-T shaped pattern and said second pattern are composed of a plurality of spacer patterns spaced apart from each other and extending in said second direction. 2 . The semiconductor pattern for monitoring overlay and critical dimension at post-etching stage of claim 1 , wherein said first inverted-T shaped pattern is symmetric with respect to said middle portion. 3 . The semiconductor pattern for monitoring overlay and critical dimension at post-etching stage of claim 1 , wherein said spacer patterns are self-aligned double patterns.
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- What does patent US2018374765A1 cover?
- A semiconductor pattern for monitoring overlay and critical dimension at post-etching stage is provided in the present invention, which include a first inverted-T shaped pattern with a base portion and a middle portion extending from the base portion and a second pattern adjacent and spaced apart from the base portion of the first inverted-T shaped pattern, wherein the first inverted-T shaped p…
- Who is the assignee on this patent?
- United Microelectronics Corp, Fujian Jinhua Integrated Circuit Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10P74/27. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Dec 27 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).