Measurement mark and method for monitoring semiconductor process

Patent metadata

Field	Value
Publication number	US-10177094-B1
Application number	US-201815954591-A
Country	US
Kind code	B1
Filing date	Apr 16, 2018
Priority date	Mar 22, 2018
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

First claim

What is claimed is:

1. A measurement mark, comprising:
a plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, wherein each of the first inner pattern blocks comprises a plurality of line patterns extending along a first direction and a block pattern having a plurality of space patterns arranged therein, wherein each of the first middle pattern blocks comprises a plurality of line patterns extending along the first direction and a block pattern having a plurality of space patterns arranged therein;
a first spacer pattern disposed along a periphery of each of the line patterns; and
a second spacer pattern disposed along a periphery of each of the space patterns.

2. The measurement mark according to claim 1 further comprising four rectangular regions arranged in a 2×2 array about a center, wherein the four rectangular regions comprise a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally, wherein the plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks are disposed within the first region.

3. The measurement mark according to claim 2 further comprising a plurality sets of second inner pattern blocks, second middle pattern blocks, and second outer reference pattern blocks disposed within the second region, wherein the plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks within the first region are rotationally symmetrical to the plurality sets of second inner pattern blocks, second middle pattern blocks, and second outer reference pattern blocks within the second region.

4. The measurement mark according to claim 1 , wherein the plurality of line patterns is arranged at a first pitch and the plurality of space patterns is arranged at a second pitch.

5. The measurement mark according to claim 4 , wherein the first pitch is equal to the second pitch.

6. The measurement mark according to claim 4 , wherein the block pattern has a first longer side and a second longer side parallel to each other, wherein the first longer side is located between the plurality of space patterns and the plurality of line patterns.

7. The measurement mark according to claim 6 , wherein a distance from the second longer side to the plurality of space patterns is greater than three times the second pitch.

8. The measurement mark according to claim 1 further comprising a third spacer pattern disposed along the periphery of each of the block patterns and surrounding the second spacer patterns.

9. The measurement mark according to claim 1 , wherein a width of the first spacer pattern is greater than that of the second spacer pattern.

10. The measurement mark according to claim 3 , wherein the third region and the fourth region comprise a plurality of line patterns extending along a second direction.

11. The measurement mark according to claim 1 , wherein the first inner pattern blocks are rotationally symmetrical to the first middle pattern block.

12. The measurement mark according to claim 1 , wherein the first inner pattern blocks, the first middle pattern blocks, and the first outer reference pattern blocks are disposed in a current layer on a wafer.

13. The measurement mark according to claim 1 , wherein the first inner pattern blocks and the first middle pattern blocks are disposed in a current layer on a wafer, and the first outer reference pattern blocks are disposed in a pre-layer or a post-layer.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Hsu Hsiao-Lin
• Liou En-Chiuan
• Chen Yi-Ting
• Lee Sho-Shen

Classifications

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title