Method for monitoring semiconductor process

Patent metadata

Field	Value
Publication number	US-10373915-B1
Application number	US-201816202104-A
Country	US
Kind code	B1
Filing date	Nov 28, 2018
Priority date	Mar 22, 2018
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

First claim

What is claimed is:

1. A method for monitoring a semiconductor process, comprising:
providing a wafer having thereon a material layer;
performing a semiconductor process comprising forming a measurement mark in the material layer, wherein the measurement mark comprises four rectangular regions arranged in a 2×2 array about a center, wherein the four rectangular regions comprise a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally, wherein a plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks is disposed in the first region, wherein each of the first inner pattern blocks comprises a plurality of line patterns extending along a first direction and a block pattern having a plurality of space patterns arranged therein, wherein each of the first middle pattern blocks comprises a plurality of line patterns extending along the first direction and a block pattern having a plurality of space patterns arranged therein, wherein the first inner pattern blocks are is rotationally symmetrical to the first middle pattern blocks;
measuring a first offset between the first inner pattern blocks and the first outer reference pattern blocks; and
measuring a second offset between the first middle pattern blocks and the first outer reference pattern blocks.

2. The method according to claim 1 , wherein the measurement mark further comprises a plurality sets of second inner pattern blocks, second middle pattern blocks, and second outer reference pattern blocks disposed within the second region, wherein the plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks within the first region is rotationally symmetrical to the plurality sets of second inner pattern blocks, second middle pattern blocks, and second outer reference pattern blocks within the second region.

3. The method according to claim 2 further comprising:
measuring a third offset between the second inner pattern blocks and the second outer reference pattern blocks; and
measuring a fourth offset between the second middle pattern blocks and the second outer reference pattern blocks.

4. The method according to claim 1 , wherein the block pattern has a first longer side and a second longer side parallel to each other, wherein the first longer side is located between the plurality of space patterns and the plurality of line patterns.

5. The method according to claim 1 , wherein the first inner pattern blocks, the first middle pattern blocks, and the first outer reference pattern blocks are disposed in a current layer on the wafer.

6. The method according to claim 1 , wherein the first inner pattern blocks and the first middle pattern blocks are disposed in a current layer on the wafer, and the first outer reference pattern blocks are disposed in a pre-layer or a post-layer.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Hsu Hsiao-Lin
• Liou En-Chiuan
• Chen Yi-Ting
• Lee Sho-Shen

Classifications

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title