Dynamic random access memory structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-2019273083-A1
Application number	US-201815936396-A
Country	US
Kind code	A1
Filing date	Mar 26, 2018
Priority date	Mar 1, 2018
Publication date	Sep 5, 2019
Grant date	—

Abstract

The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

First claim

1 . A dynamic random access memory (DRAM) structure, comprising:
a substrate having a cell region and a peripheral region defined thereon; a plurality of buried word lines, located in the cell region of the substrate; a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface; a first dummy bit line gate located on the shallow trench isolation structure within the peripheral area; and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

2 . The dynamic random access memory structure of claim 1 , wherein the first dummy bit line gate is completely located on the shallow trench isolation structure.

3 . The dynamic random access memory structure of claim 1 , further comprising a dielectric layer disposed on the substrate and on the shallow trench isolation structure.

4 . The dynamic random access memory structure of claim 3 , wherein a portion of the dielectric layer is located between the first dummy bit line gate and the second dummy bit line gate.

5 . The dynamic random access memory structure of claim 1 , wherein the first dummy bit line gate contacts the second dummy bit line gate directly.

6 . (canceled)

7 . The dynamic random access memory structure of claim 1 , wherein the first dummy bit line gate comprises a stacked structure of an amorphous silicon layer, a barrier layer and a metal layer.

8 . A method for forming a dynamic random access memory (DRAM) structure, comprising:
providing a substrate having a cell region and a peripheral region defined thereon; forming a plurality of buried word lines in the cell region of the substrate; forming a shallow trench isolation structure in the peripheral region adjacent to the cell region performing a first etching step to form a concave top surface on the shallow trench isolation structure; forming a first dummy bit line gate on the shallow trench isolation structure within the peripheral area; and forming a second dummy bit line gate in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.

9 . The method of claim 8 , wherein the first dummy bit line gate and the second dummy bit line gate are formed simultaneously.

10 . The method of claim 8 , wherein the method for forming the first dummy bit line gate and the second dummy bit line gate comprising:
forming a stack structure within the cell region and on the shallow trench isolation structure; and performing a second etching step, to pattern the stack structure and to form the first dummy bit line gate and the second dummy bit line gate.

11 . The method of claim 8 , further comprising forming a mask layer on the first dummy bit line gate.

12 . The method of claim 11 , wherein the material of the mask layer contains silicon oxide.

13 . The method of claim 11 , further comprising forming a dielectric layer covering the first dummy bit line gate and the second dummy bit line gate after the first dummy bit line gate and the second dummy bit line gate are patterned.

14 . The method of claim 13 , further comprising performing a planarization step to remove a portion of the dielectric layer and completely remove the mask layer at the top of the first dummy bit line gate.

15 . The method of claim 13 , wherein a portion of the dielectric layer is located between the first dummy bit line gate and the second dummy bit line gate.

16 . The method of claim 8 , wherein the first dummy bit line gate contacts the second dummy bit line gate directly.

17 . (canceled)

18 . The method of claim 8 , wherein the first dummy bit line gate is completely located on the shallow trench isolation structure.

19 . The method of claim 8 , further comprising forming a plurality of spacers on sidewalls of the first dummy bit line gate and the second dummy bit line gate.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Liou En-Chiuan
• Tung Yu-Cheng
• Yang Chih-Wei
• Lee Sho-Shen

Classifications

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• H01L27/10844

  Electricity · mapped topic

• H01L27/10897 Primary

  Electricity · mapped topic

• H10B12/00

  Dynamic random access memory [DRAM] devices · CPC title

• H10B12/09 Primary

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title