Method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2018286692-A1
Application number	US-201815928078-A
Country	US
Kind code	A1
Filing date	Mar 21, 2018
Priority date	Mar 29, 2017
Publication date	Oct 4, 2018
Grant date	—

Abstract

The present invention provides a method for manufacturing a semiconductor device including following steps. A substrate, a hard mask layer disposed on the substrate and a first mask pattern disposed on the hard mask layer are provided, and the substrate has a device region and a cutting line region. The first mask pattern has first gaps in the device region and second gaps in the cutting line region. Next, a spacer layer conformally covers the first mask pattern. Then, a second mask pattern is formed on the spacer layer in the first gaps, and a top surface of the second mask pattern is lower than a top surface of the first mask pattern. Thereafter, an etching process is performed to the spacer layer to remove the spacer layer between the first mask layer and the second mask layer and in the second gaps and expose the hard mask layer.

First claim

What is claimed is:

1 . A method for manufacturing a semiconductor device, comprising:
providing a substrate, a hard mask layer and a first mask pattern, wherein the substrate has a device region and a cutting line region, the hard mask layer is disposed on the substrate, and the first mask pattern is disposed on the hard mask layer, and wherein the first mask pattern comprises a plurality of strip-shaped device patterns and a plurality of strip-shaped alignment patterns, each strip-shaped device pattern is disposed along a first direction in the device region, the strip-shaped device patterns are arranged along a second direction, each strip-shaped alignment pattern is disposed along the first direction in the cutting line region, the strip-shaped alignment patterns are arranged along the second direction, a first gap exists between any two of the strip-shaped device patterns adjacent to each other, a second gap exists between any two of the strip-shaped alignment patterns adjacent to each other, and a width of each second gap is greater than a width of each first gap; forming a spacer layer to conformally cover the first mask pattern; forming a second mask pattern on the spacer layer in the first gaps, wherein a top surface of the second mask pattern is lower than a top surface of the first mask pattern; performing a first etching process on the spacer layer to remove a part of the spacer layer between the first mask pattern and the second mask pattern and another part of the spacer layer in the second gaps so as to expose the hard mask layer; using the first hard mask pattern and the second mask pattern as a mask to pattern the hard mask layer so as to form a hard mask pattern; and using the hard mask pattern as another mask to etch the substrate so as to form a plurality of first trenches and a plurality of second trenches in the substrate, wherein a depth of each second trench is greater than a depth of each first trench.

2 . The method for manufacturing the semiconductor device according to claim 1 , wherein the width of each second gap is 20 times greater than the width of each first gap.

3 . The method for manufacturing the semiconductor device according to claim 1 , wherein forming the second mask pattern comprises:
forming a mask material layer on the spacer layer, wherein the mask material layer fills up the first gaps and the second gaps; and performing a second etching process on the mask material layer to remove apart of the mask material layer on the first mask pattern and another part of the mask material layer in the second gaps so as to form the second mask pattern in the first gaps, wherein the second mask pattern comprises a plurality of blocks in the first gaps respectively.

4 . The method for manufacturing the semiconductor device according to claim 1 , wherein the first etching process further comprises removing a part of the hard mask layer exposed by each second gap to form a plurality of first recesses on the hard mask layer.

5 . The method for manufacturing the semiconductor device according to claim 4 , wherein the substrate comprises a semiconductor substrate, an oxide layer and a pattern transferring layer, and the oxide layer and the pattern transferring layer are sequentially stacked on the semiconductor substrate, and wherein patterning the hard mask pattern further comprises forming a plurality of second recesses on the pattern transferring layer, and the second recesses correspond to the first recesses respectively.

6 . The method for manufacturing the semiconductor device according to claim 5 , wherein etching the substrate comprises etching the pattern transferring layer and the oxide layer to form a transfer pattern and an oxide pattern and expose the semiconductor substrate.

7 . The method for manufacturing the semiconductor device according to claim 6 , further comprising:
removing the hard mask pattern after forming the transfer pattern and the oxide pattern; and performing a third etching process to etch the exposed semiconductor substrate to form a plurality of third trenches and a plurality of fourth trenches on the semiconductor substrate, wherein the third trenches are disposed in the device region, the fourth trenches are disposed in the cutting line region, and a depth of each fourth trench is greater than a depth of each third trench.

8 . The method for manufacturing the semiconductor device according to claim 1 , wherein a third gap exists between one of the strip-shaped alignment patterns closest to the strip-shaped device patterns and one of the strip-shaped device patterns closest to the strip-shaped alignment patterns, a width of the third gap is greater than the width of each first gap, etching the substrate comprises forming a fifth trench in the substrate corresponding to the third gap.

9 . The method for manufacturing the semiconductor device according to claim 1 , wherein providing the first mask pattern comprises:
sequentially forming an organic layer and a silicon-containing layer to cover the hard mask layer; forming a photoresist pattern on the silicon-containing layer; using the photoresist pattern as another mask to pattern the silicon-containing layer; and patterning the organic layer and removing the photoresist pattern to form the first mask pattern.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Chen Chien-Hao
• Wu Feng-Lun
• Hsia Chung-Ping
• Lee Sho-Shen

Classifications

• H10P76/2043

  using an anti-reflective coating · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title