Method of forming overlay mark structure

US10529667B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10529667-B1
Application numberUS-201816049826-A
CountryUS
Kind codeB1
Filing dateJul 31, 2018
Priority dateJul 5, 2018
Publication dateJan 7, 2020
Grant dateJan 7, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming an overlay mark structure, comprising: forming an insulation layer on a substrate; forming a first overlay mark in the insulation layer; forming a metal layer on the substrate, wherein the metal layer covers the insulation layer and the first overlay mark; removing the metal layer on the first overlay mark, wherein a top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark; and forming a second overlay mark on the metal layer. 2. The method of forming the overlay mark structure according to claim 1 , wherein a projection pattern of the first overlay mark in a thickness direction of the substrate surrounds at least a part of a projection pattern of the second overlay mark in the thickness direction of the substrate. 3. The method of forming the overlay mark structure according to claim 1 , wherein a main region and an overlay mark region are defined on the substrate, and the first overlay mark and the second overlay mark are formed on the overlay mark region. 4. The method of forming the overlay mark structure according to claim 3 , further comprising: forming isolation structures on the main region; and forming a storage node contact structure between two of the isolation structures adjacent to each other, wherein the first overlay mark and the isolation structures are formed concurrently by the same process. 5. The method of forming the overlay mark structure according to claim 4 , wherein a material composition of the first overlay mark is identical to a material composition of the isolation structures. 6. The method of forming the overlay mark structure according to claim 5 , wherein the first overlay mark comprises an insulation material. 7. The method of forming the overlay mark structure according to claim 4 , wherein the metal layer is further formed on the storage node contact structure. 8. The method of forming the overlay mark structure according to claim 7 , further comprising: forming a patterned mask layer on the metal layer on the main region, wherein the patterned mask layer and the second overlay mark are formed concurrently by the same process. 9. The method of forming the overlay mark structure according to claim 8 , wherein a material composition of the second overlay mark is identical to a material composition of the patterned mask layer. 10. The method of forming the overlay mark structure according to claim 9 , wherein the second overlay mark comprises a photoresist material. 11. The method of forming the overlay mark structure according to claim 8 , further comprising: performing a patterning process to the metal layer on the main region with the patterned mask layer as a mask, wherein a least a part of the metal layer on the main region is patterned to be a storage node pad on the storage node contact structure. 12. The method of forming the overlay mark structure according to claim 1 , further comprising: forming an anti-reflection layer covering the metal layer, the first overlay mark and the insulation layer after the step of removing the metal layer on the first overlay mark and before the step of forming the second overlay mark, wherein the second overlay mark is formed on the anti-reflection layer. 13. The method of forming the overlay mark structure according to claim 1 , further comprising: forming a cap layer on the metal layer before the step of removing the metal layer on the first overlay mark, wherein a part of the cap layer overlaps the first overlay mark; and removing the cap layer above the first overlay mark before the step of forming the second overlay mark. 14. The method of forming the overlay mark structure according to claim 13 , wherein a part of the cap layer is located between the second overlay mark and the metal layer in a thickness direction of the substrate.

Assignees

Inventors

Classifications

  • using an anti-reflective coating · CPC title

  • using masks for insulating materials · CPC title

  • using masks for conductive or resistive materials · CPC title

  • for alignment · CPC title

  • H10W46/00Primary

    Marks applied to devices, e.g. for alignment or identification · CPC title

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What does patent US10529667B1 cover?
A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower th…
Who is the assignee on this patent?
United Microelectronics Corp, Fujian Jinhua Integrated Circuit Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W46/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 07 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).