Method of forming layout of semiconductor device

Patent metadata

Field	Value
Publication number	US-10707213-B2
Application number	US-201816178521-A
Country	US
Kind code	B2
Filing date	Nov 1, 2018
Priority date	Oct 9, 2018
Publication date	Jul 7, 2020
Grant date	Jul 7, 2020

Abstract

A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

First claim

What is claimed is:

1. A method of forming a layout of a semiconductor device, comprising:
forming a plurality of first line patterns being long straight lines in each areas, wherein the first line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area between the first area and the second area, wherein the second direction is different from the first direction;
forming a plurality of second line patterns being long straight lines in each areas, wherein the second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area between the first area and the second area, wherein the fourth direction is different from the third direction, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area; and
performing a trimming process to shade the first line patterns and the second line patterns in the boundary area and the second area.

2. The method of forming a layout of a semiconductor device according to claim 1 , wherein the overlapping areas are distributed along a horizontal direction and along a vertical direction, and a pattern area is divided into the first area, the boundary area and the second area at the vertical direction.

3. The method of forming a layout of a semiconductor device according to claim 2 , wherein an acute angle between the second direction and the horizontal direction is larger than an acute angle between the first direction and the horizontal direction.

4. The method of forming a layout of a semiconductor device according to claim 3 , wherein the acute angle between the first direction and the horizontal direction is 30°, and the acute angle between the second direction and the horizontal direction is larger than 30° but less than 90°.

5. The method of forming a layout of a semiconductor device according to claim 2 , wherein an acute angle between the fourth direction and the horizontal direction is larger than an acute angle between the third direction and the horizontal direction.

6. The method of forming a layout of a semiconductor device according to claim 5 , wherein the acute angle between the third direction and the horizontal direction is 30°, and the acute angle between the fourth direction and the horizontal direction is larger than 30° but less than 90°.

7. The method of forming a layout of a semiconductor device according to claim 1 , wherein the trimming process is performed by forming a patterned photoresist to cover the first line patterns and the second line patterns in the boundary area and the second area.

8. The method of forming a layout of a semiconductor device according to claim 7 , wherein an edge of the patterned photoresist in the boundary area is a serrated edge.

9. The method of forming a layout of a semiconductor device according to claim 8 , wherein acute angles between the serrated edge of the patterned photoresist and the horizontal direction are larger than an acute angle between the first direction and the horizontal direction, and larger than an acute angle between the third direction and the horizontal direction, but are less than an acute angle between the second direction and the horizontal direction, and less than an acute angle between the fourth direction and the horizontal direction.

10. The method of forming a layout of a semiconductor device according to claim 1 , further comprising:
forming a plurality of first spacer patterns surrounding the first line patterns after the first line patterns are formed, and then removing the first line patterns.

11. The method of forming a layout of a semiconductor device according to claim 10 , further comprising:
forming a plurality of second spacer patterns surrounding the second line patterns after the second line patterns are formed, and then removing the second line patterns.

12. The method of forming a layout of a semiconductor device according to claim 11 , wherein the trimming process is performed after the first spacer patterns and the second spacer patterns are formed.

13. The method of forming a layout of a semiconductor device according to claim 12 , wherein the overlapping areas comprise holes enclosed by the first spacer patterns and the second spacer patterns.

14. The method of forming a layout of a semiconductor device according to claim 13 , wherein the holes comprise rhombus holes.

15. The method of forming a layout of a semiconductor device according to claim 11 , wherein the first spacer patterns and the second spacer patterns are in different layers.

16. The method of forming a layout of a semiconductor device according to claim 12 , wherein the first spacer patterns and the second spacer patterns are on a hard mask layer.

17. The method of forming a layout of a semiconductor device according to claim 16 , further comprising:
etching the hard mask layer exposed by the overlapping areas to form a mask pattern, and then transferring the mask pattern into a storage node layer to form a storage node pattern.

18. The method of forming a layout of a semiconductor device according to claim 17 , wherein the hard mask layer comprises a hard mask layer of a storage node layer in a dynamic random access memory area.

19. The method of forming a layout of a semiconductor device according to claim 18 , wherein the first area comprises a storage node pattern area while the second area comprises a storage node spare pattern area.

20. The method of forming a layout of a semiconductor device according to claim 16 , wherein the hard mask layer comprises a stacked hard mask layer.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Wang Chia-Hung
• Liou En-Chiuan
• Chen Chien-Hao
• Lee Sho-Shen
• Chen Yi-Ting
• Lee Jhao-Hao

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/067

  by modifying the pattern of conductive parts · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title