Acceleration of data queries in memory
US-2025349364-A1 · Nov 13, 2025 · US
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Helm Mark A patents
Helm Mark A is listed as an inventor on 105 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Helm Mark A |
| Total patents | 105 |
| First publication | Mar 5, 2015 |
| Latest publication | Nov 13, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatus having transistors with raised extension regions and semiconductor fins
US-2025267860-A1 · Aug 21, 2025 · US
Acceleration of data queries in memory
US-12367935-B2 · Jul 22, 2025 · US
Ultra-high endurance storage class memory as a host data buffer in a memory sub-system
US-2025190140-A1 · Jun 12, 2025 · US
Ultra-high endurance storage class memory as a program buffer in a memory sub-system
US-2025190123-A1 · Jun 12, 2025 · US
Ultra-high endurance storage class memory to reduce storage capacitance in a memory sub-system
US-2025190122-A1 · Jun 12, 2025 · US
Adjustment of code rate as function of memory endurance state metric
US-12326782-B2 · Jun 10, 2025 · US
Transistors with raised extension regions and semiconductor fins
US-12310010-B2 · May 20, 2025 · US
Status check using chip enable pin
US-2025094364-A1 · Mar 20, 2025 · US
Status check using chip enable pin
US-12169461-B2 · Dec 17, 2024 · US
Recent patents
Latest publications not already listed above.
Implementing variable number of bits per cell on storage devices
US-12086466-B2 · Sep 10, 2024 · US
Adjustment of code rate as function of memory endurance state metric
US-2024232013-A1 · Jul 11, 2024 · US
Partitioned memory having error detection capability
US-12026052-B2 · Jul 2, 2024 · US
Adjustment of code rate as function of memory endurance state metric
US-11983067-B2 · May 14, 2024 · US
Acceleration of data queries in memory
US-2024105264-A1 · Mar 28, 2024 · US
Multi-layer code rate architecture for copyback between partitions with different code rates
US-2024086282-A1 · Mar 14, 2024 · US
Adjustment of code rate as function of memory endurance state metric
US-2024070023-A1 · Feb 29, 2024 · US
Implementing fault tolerant page stripes on low density memory systems
US-11899966-B2 · Feb 13, 2024 · US
Multi-layer code rate architecture for copyback between partitions with different code rates
US-11829245-B2 · Nov 28, 2023 · US
Acceleration of data queries in memory
US-11823742-B2 · Nov 21, 2023 · US
Acceleration of data queries in memory
US-11797531-B2 · Oct 24, 2023 · US
Separate partition for buffer and snapshot memory
US-11789629-B2 · Oct 17, 2023 · US
Threshold voltage based on program/erase cycles
US-11776629-B2 · Oct 3, 2023 · US
Partitions within snapshot memory for buffer and snapshot memory
US-11775208-B2 · Oct 3, 2023 · US
Multi-layer code rate architecture for copyback between partitions with different code rates
US-2023297470-A1 · Sep 21, 2023 · US
Read voltage calibration for copyback operation
US-11694763-B2 · Jul 4, 2023 · US
Implementing variable number of bits per cell on storage devices
US-2023205463-A1 · Jun 29, 2023 · US
Threshold voltage distribution adjustment for buffer
US-11663104-B2 · May 30, 2023 · US
Implementing variable number of bits per cell on storage devices
US-11640262-B2 · May 2, 2023 · US
Acceleration of data queries in memory
US-11635906-B2 · Apr 25, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 101 |
| Lodestar Licensing Group Llc | 4 |
| Kalavade Pranav | 2 |
| Helm Mark A | 2 |
| Goldman Matthew | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C16/0483 | 45 |
| G06F3/0679 | 39 |
| G11C16/26 | 33 |
| G06F3/061 | 27 |
| G06F11/1048 | 26 |