Implementing variable number of bits per cell on storage devices

Patent metadata

Field	Value
Publication number	US-11640262-B2
Application number	US-202016868868-A
Country	US
Kind code	B2
Filing date	May 7, 2020
Priority date	May 7, 2020
Publication date	May 2, 2023
Grant date	May 2, 2023

Abstract

Systems and methods are disclosed including a memory component and a processing device, coupled to the memory component. The processing device can program a block of the memory component using a first type of memory cells storing a first number of bits per memory cell. The processing device can then determine that an amount of memory used of the memory component is greater than a capacity threshold. Responsive to determining that a frequency of access to the block meets a criterion, the processing device can then program the block using a second type memory cells storing a second number of bits per memory cell, wherein the second number of bits exceeds the first number of bits.

First claim

What is claimed is:

1. A system comprising:
a memory component; and
a processing device, coupled to the memory component, configured to:
responsive to receiving first data to program to a block of the memory component, determine a current mode of operation used by the system to program data to the block;
responsive to determining that the current mode of operation is a first mode of operation, program the first data to a set of memory cells of the block using a first type of memory cells storing a first number of bits per memory cell;
responsive to receiving second data to program to the block; determine that an amount of memory used of the memory component is greater than a capacity threshold;
responsive to determining that a frequency of access to the block meets a criterion, select a new mode of operation to be used by the processing device to program the second data to the block, wherein the system in the new mode of operation utilizes a second type of memory cells storing a second number of bits per memory cell, wherein the second number of bits exceeds the first number of bits; and
reprogram, using the new mode of operation, the block storing the first data by programming second data to the set of memory cells while maintaining the first data programmed to the set of memory cells, thus converting the set of memory cells to the second type of memory cells that stores the second number of bits per memory cell.

2. The system of claim 1 , wherein the first type of memory cells comprises single level cells (SLCs).

3. The system of claim 1 , wherein the second type of memory cells comprises at least one of: multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), or penta-level cells (PLC).

4. The system of claim 1 , wherein programing the block using the second type of memory cells comprises: combining bits of data from each memory cell of the block into memory cells of the second type of memory cells.

5. The system of claim 1 , wherein the frequency of access comprises at least one of: a duration of time between two consequent accesses operations, a duration of time between a write operation and a read operation, or a rate of access within a time period.

6. The system of claim 1 , wherein the processing device is further configured to: receive an indication from a host system comprising an expected frequency of access to the block.

7. The system of claim 1 , wherein the first number of bits per memory cell utilized is reverse proportional the frequency of access.

8. A method comprising:
responsive to receiving first data to program to a block of a memory component, determining a current mode of operation used to program data to the block;
responsive to determining that the current mode of operation is a first mode of operation, programming the first data to a set of memory cells of the block using a first type of memory cells storing a first number of bits per memory cell;
responsive to receiving second data to program to the block; determining that an amount of memory used of the memory component is greater than a capacity threshold;
responsive to determining that a frequency of access to the block meets a criterion, selecting a new mode of operation to be used by the processing device to program the second data to the block, wherein the system in the new mode of operation utilizes a second type of memory cells storing a second number of bits per memory cell, wherein the second number of bits exceeds the first number of bits; and
reprogramming, using the new mode of operation, the block storing the first data by programming second data to the set of memory cells while maintaining the first data programmed to the set of memory cells, thus converting the set of memory cells to the second type of memory cells that stores the second number of bits per memory cell.

9. The method of claim 8 , wherein the first type of memory cells comprises single level cells (SLCs).

10. The method of claim 8 , wherein the second type of memory cells comprises at least one of: multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), or penta-level cells (PLC).

11. The method of claim 8 , wherein the frequency of access comprises at least one of: a duration of time between two consequent accesses operations, a duration of time between a write operation and a read operation, or a rate of access within a time period.

12. The method of claim 8 , wherein the memory component comprises of a first set of single level cells (SLCs), a second set of multi-level cells (MLCs), a third set of triple level cells (TLCs), and a fourth set of quad-level cells (QLCs).

13. The method of claim 8 , further comprising: receiving an indication from a host system comprising an expected frequency of access to the block.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
responsive to receiving first data to program to a block of a memory component, determine a current mode of operation used to program data to the block;
responsive to determining that the current mode of operation is a first mode of operation, program the first data to a set of memory cells of the block using a first type of memory cells storing a first number of bits per memory cell;
responsive to receiving second data to program to the block; determine that an amount of memory used of the memory component is greater than a capacity threshold;
responsive to determining that a frequency of access to the block meets a criterion, select a new mode of operation to be used by the processing device to program the second data to the block, wherein the system in the new mode of operation utilizes a second type of memory cells storing a second number of bits per memory cell, wherein the second number of bits exceeds the first number of bits; and
reprogram, using the new mode of operation, the block storing the first data by programming second data to the set of memory cells while maintaining the first data programmed to the set of memory cells, thus converting the set of memory cells to the second type of memory cells that stores the second number of bits per memory cell.

15. The non-transitory computer-readable storage medium of claim 14 , wherein the first type of memory cells comprises single level cells (SLCs).

16. The non-transitory computer-readable storage medium of claim 14 , wherein the second type of memory cells comprises at least one of: multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), or penta-level cells (PLC).

17. The non-transitory computer-readable storage medium of claim 14 , wherein the frequency of access comprises at least one of: a duration of time between two consequent accesses operations, a duration of time between a write operation and a read operation, or a rate of access within a time period.

Assignees

• Micron Technology Inc

Inventors

• Helm Mark A

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title

• G06F3/0608

  Saving storage space on storage systems · CPC title