Acceleration of data queries in memory

Patent metadata

Field	Value
Publication number	US-11823742-B2
Application number	US-202217704687-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Aug 4, 2020
Publication date	Nov 21, 2023
Grant date	Nov 21, 2023

Abstract

The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of memory cells; and
processing circuitry configured to:
receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host;
search portions of the array of memory cells for the particular data corresponding to the search key;
count a quantity of bits in each of the portions of the array of memory cells that match a corresponding bit in the search key;
compare the quantity of bits in each respective portion of the array of memory cells that match the corresponding bit in the search key to a mismatch bit count for the query;
determine whether data stored in each respective portion of the array matches the query based on the comparison; and
transfer the data that matches the query to the host.

2. The apparatus of claim 1 , wherein the processing circuitry is configured to refrain from transferring data that does not match the query to the host.

3. The apparatus of claim 1 , wherein:
the bits in each of the portions of the array of memory cells are encrypted; and
the processing circuitry is configured to decrypt the encrypted bits.

4. The apparatus of claim 1 , wherein the processing circuitry is configured to determine the data stored in a respective portion of the array does not match the query upon the comparison indicating the quantity of bits in that respective portion is lower than the mismatch bit count.

5. The apparatus of claim 1 , wherein the processing circuitry is configured to determine the data stored in a respective portion of the array does not match the query upon the comparison indicating the quantity of bits in that respective portion is greater than the mismatch bit count.

6. The apparatus of claim 1 , wherein the mismatch bit count is set by the host.

7. The apparatus of claim 1 , wherein the processing circuitry is configured to count the quantity of bits in a respective portion of the array of memory cells that match the corresponding bit in the search key based on an amount of current conducted by that respective portion when a current is applied to that respective portion.

8. The apparatus of claim 1 , wherein the processing circuitry is configured to count the quantity of bits in a respective portion of the array of memory cells that match the corresponding bit in the search key based on an amount of current conducted by that respective portion when a voltage is applied to that respective portion.

9. A method, comprising:
receiving, by a memory device from a host, a query for particular data, wherein the particular data corresponds to a search key generated by the host;
searching, by the memory device, portions of the memory device for the particular data, wherein the searching includes:
sensing, by the memory device, data stored in the portions of the memory device;
performing, by the memory device, an error correction operation on the sensed data; and
decrypting, by the memory device, the sensed data after performing the error correction operation on the sensed data;

counting, by the memory device, a quantity of bits in each of the portions of the memory device that match a corresponding bit in the search key to determine data stored in the portions of the memory device that matches the query; and
transferring the data that matches the query to the host.

10. The method of claim 9 , wherein the method includes performing the error correction operation on the sensed data using an error correction code stored in the memory device.

11. The method of claim 9 , wherein the method includes performing the error correction operation on the sensed data by error correction code (ECC) circuitry of the memory device.

12. The method of claim 9 , wherein the method includes decrypting the sensed data by encryption/decryption circuitry of the memory device.

13. The method of claim 9 , wherein the method includes decrypting the sensed data using a decryption algorithm.

14. The method of claim 9 , wherein the method includes:
searching the portions of the memory device for the particular data using circuitry that is resident on the memory device; and
counting the quantity of bits in each of the portions of the memory device that match the corresponding bit in the search key using the circuitry that is resident on the memory device.

15. The method of claim 9 , wherein the method includes:
searching each of the portions of the memory device for the particular data in parallel; and
counting the quantity of bits in each of the portions of the memory device that match the corresponding bit in the search key in parallel.

16. A method, comprising:
generating, by a host, a search key denoting particular data;
sending, to a memory device by the host, a query for the particular data; and
receiving data that matches the query at the host, wherein:
the data that matches the query is based at least in part on results of a search at the memory device that includes a comparison of the search key and determination of matching data, relative to the search key, stored within the memory device; and
the data that matches the query comprises data whose quantity of bits that match a corresponding bit in the search key is greater than a mismatch bit count for the query.

17. The method of claim 16 , wherein the method includes receiving the data that matches the query at the host from the memory device.

18. The method of claim 16 , wherein the method includes receiving the data that matches the query at the host from a buffer coupled to the host.

19. The method of claim 16 , wherein the data that matches the query comprises data that exactly matches the query.

Assignees

• Micron Technology Inc

Inventors

• Helm Mark A
• Pawlowski Joseph T

Classifications

• G11C16/12 Primary

  Programming voltage switching circuits · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C2029/0411

  Online error correction · CPC title