Partitioned memory having error detection capability

Patent metadata

Field	Value
Publication number	US-12026052-B2
Application number	US-202217971346-A
Country	US
Kind code	B2
Filing date	Oct 21, 2022
Priority date	Aug 17, 2020
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

First claim

What is claimed is:

1. A system, comprising:
a memory component comprising:
a first memory portion, wherein the first memory portion is a cyclic buffer partition portion;
a second memory portion; and
a power supply to supply power to the cyclic buffer partition portion and the second memory portion in response to a signal that a trigger event has occurred; and

a processing device included in the memory component to, in response to receiving the signal that a trigger event has occurred:
perform an error correction operation on a portion of data stored in the cyclic buffer partition portion;
copy the data stored in the cyclic buffer partition portion to the second memory portion in response to the error correction operation being successful; and
send the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

2. The system of claim 1 , wherein the power supply comprises hold-up capacitors.

3. The system of claim 1 , wherein the power supply is a non-volatile power supply.

4. The system of claim 1 , wherein the power supply is a battery.

5. The system of claim 1 , wherein the power supply is to supply the power to the cyclic buffer partition portion and the second memory portion for a duration sufficient to copy at least the portion of the data stored in the cyclic buffer partition portion to the second memory portion.

6. The system of claim 1 , wherein the power supply is to supply the power to the cyclic buffer partition portion and the second memory portion for a duration sufficient to copy all the data stored in the cyclic buffer partition portion to the second memory portion.

7. The system of claim 1 , wherein the trigger event comprises a sensor of a vehicle host detecting that the vehicle host has been involved in a vehicular accident.

8. The system of claim 1 , wherein:
the second memory portion is a snapshot partition portion.

9. The system of claim 1 , wherein:
the cyclic buffer partition portion comprises single level memory cells; and
the second memory portion comprises multiple level memory cells.

10. A method, comprising:
receiving, by a memory component of a memory sub-system, a signal that a trigger event has occurred from a processing device of the memory sub-system operatively coupled to the memory component;
supplying, by a power supply of the memory component, power to a first memory portion of the memory component and a second memory portion of the memory component in response to the memory component receiving the signal, wherein the first memory portion is a cyclic buffer partition portion;
performing, by the memory component in response to receiving the signal, an error correction operation on a portion of data stored in the cyclic buffer partition portion of the memory component, wherein performing the error correction operation comprises determining whether a quantity of erroneous data in the portion of data is less than a threshold quantity;
copying, by the memory component in response to the error correction operation being successful, the data stored in the cyclic buffer partition portion to the second memory portion of the memory component; and
sending, by the memory component in response to the error correction operation not being successful, the data stored in the cyclic buffer partition portion to the processing device.

11. The method of claim 10 , wherein the threshold quantity is a pre-defined threshold quantity.

12. The method of claim 10 , wherein the error correction operation is successful if it is determined the quantity of erroneous data in the portion of data is less than the threshold quantity.

13. The method of claim 10 , wherein the error correction operation is not successful if it is determined the quantity of erroneous data in the portion of data is not less than the threshold quantity.

14. The method of claim 10 , wherein the method includes receiving, by the processing device, the signal from a sensor of a vehicle host responsive to the sensor detecting that the vehicle host has been involved in a vehicular accident.

15. The method of claim 14 , wherein the vehicle host is an autonomous vehicle.

16. The method of claim 10 , wherein the method includes performing the error correction operation using parity data stored in the cyclic buffer partition portion.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a signal that a trigger event has occurred from a processing device of a memory sub-system;
supply, by a power supply of a memory component of the memory sub-system, power to a first memory portion of the memory component and a second memory portion of the memory component in response to receiving the signal, wherein the first memory portion is a cyclic buffer partition portion;
determine, in response to receiving the signal, whether a quantity of erroneous data in a portion of data stored in the cyclic buffer partition portion of a memory component of the memory sub-system is less than a threshold quantity, wherein the threshold quantity corresponds to an error correction capability of the processing device;
correct the erroneous data and copy the data stored in the cyclic buffer partition portion of the memory component to the second memory portion of the memory component in response to determining the quantity of erroneous data is less than the threshold quantity; and
send the data stored in the cyclic buffer partition portion of the memory component to the processing device in response to determining the quantity of erroneous data is not less than the threshold quantity.

18. The non-transitory computer-readable storage medium of claim 17 , wherein:
the quantity of erroneous data corresponds to a bit error rate in the portion of data; and
the threshold quantity is a threshold bit error rate.

19. The non-transitory computer-readable storage medium of claim 17 , wherein determining whether the quantity of erroneous data in the portion of data is less than the threshold quantity comprises dividing the quantity of erroneous data in the portion of data by a total quantity of data in the portion of data.

20. The non-transitory computer-readable medium of claim 17 , wherein the error correction capability of the processing device is a maximum quantity of erroneous data the processing device is capable of correcting during an error correction operation.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Muchherla Kishore K
• Righetti Niccolo'
• Mcneil Jr Jeffrey S
• Goda Akira
• Marquart Todd A
• Helm Mark A
• Golov Gil
• Binfet Jeremy
• Miccoli Carmine
• Puzzilli Giuseppina

Classifications

• G06F3/065

  Replication mechanisms · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title