Partitions within snapshot memory for buffer and snapshot memory

Patent metadata

Field	Value
Publication number	US-11775208-B2
Application number	US-202217829861-A
Country	US
Kind code	B2
Filing date	Jun 1, 2022
Priority date	Aug 17, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.

First claim

What is claimed is:

1. A system, comprising:
a processing device; and
a memory device communicatively coupled to the processing device and comprising:
a cyclic buffer portion; and
a snapshot portion coupled to the cyclic buffer portion, the snapshot portion further comprising:
a first portion having a first programming characteristic; and
a second portion having a second programming characteristic;

wherein the processing device is to:
write received data sequentially to the first portion; and
write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer to the first or second portion of the snapshot portion, or both.

2. The system of claim 1 , wherein the processing device is to:
operate memory cells of the first portion in a single-level cell (SLC) mode; and
operate memory cells of the second portion in a multiple level cell mode.

3. The system of claim 1 , wherein an energy consumption per bit associated with the first programming characteristic is less than an energy consumption per bit associated with the second programming characteristic.

4. The system of claim 1 , wherein the first portion of memory cells of the snapshot portion having the first programming characteristic are configured to store less number of bits per cell than the second portion of memory cells of the snapshot portion having the second programming characteristic.

5. The system of claim 1 , wherein the first portion has an endurance characteristic greater than that of the second portion.

6. The system of claim 1 , wherein the processing device is an advanced driver assistance system controller (ADAS).

7. The system of claim 1 , wherein the first portion of the snapshot portion comprises negative AND (NAND) memory cells having the first programming characteristic associated therewith.

8. The system of claim 1 , wherein the first portion of the snapshot portion is configured to operate as a cache for the second portion of the snapshot portion.

9. A method, comprising:
writing data sequentially received to a cyclic buffer portion of a memory device; and
responsive to a trigger event:
writing data from the cyclic buffer portion to a first portion of a snapshot portion of the memory device at a first data transfer rate corresponding to a first programming characteristic of the first portion of the snapshot portion; and
writing at least a portion of the data from the first portion of the snapshot portion to a second portion of the snapshot portion at a second data transfer rate corresponding to a second programming characteristic of the second portion of the snapshot portion, wherein the first data transfer rate is faster than the second data transfer rate.

10. The method of claim 9 , further comprising receiving the data sequentially to the cyclic buffer portion at a data transfer rate corresponding to the first programming characteristic.

11. The method of claim 9 , further comprising, subsequent to writing the at least the portion of the data to the first portion of the snapshot portion, writing the at least the portion of the data from the first portion of the snapshot portion to the second portion of the snapshot portion at the data transfer rate corresponding to the second programming characteristic.

12. The method of claim 9 , further comprising writing the data from the cyclic buffer portion to the first portion of the snapshot portion of the snapshot portion at the first data transfer rate responsive to a loss of a primary power supply coupled to the memory device.

13. The method of claim 12 , further comprising writing the at least the portion of the data from the first portion of the snapshot portion to the second portion of the snapshot portion responsive to the primary power supply being available again.

14. A system, comprising:
a processing device; and
a memory device communicatively coupled to the processing device and comprising:
a cyclic buffer portion; and
a snapshot portion coupled to the cyclic buffer portion, the snapshot portion further comprising:
a first portion having a first programming characteristic; and
a second portion having a second programming characteristic;

wherein the processing device is to, in response to a trigger event:
write a set of sequentially received data previously written to the cyclic buffer portion to the first portion of the snapshot portion at a data transfer rate corresponding to the first programming characteristic; and
provide a secondary power supply to enable writing the set of sequentially received data from the cyclic buffer portion to the first portion of the snapshot portion.

15. The system of claim 14 , wherein the processing device is to provide the secondary power supply to enable writing the set of sequentially received data from the cyclic buffer portion to the first portion of the snapshot portion in response to a loss of a primary power supply.

16. The system of claim 15 , wherein the processing device is to write the set of sequentially received data from the first portion to the second portion of the snapshot portion in response to the primary power supply being available again.

17. The system of claim 15 , wherein the processing device is to write the set of sequentially received data directly to the second portion of the snapshot portion in response to the trigger event and in response to the primary power supply being available.

18. The system of claim 14 , wherein further comprising a plurality of sensors, and wherein the set of sequentially received data are obtained from different sensors of the plurality and aggregated prior being received at the processing device.

19. The system of claim 18 , wherein the plurality of sensors comprises a camera sensor or a microphone sensor, or both.

20. The system of claim 14 , wherein the set of sequentially received data corresponds to an amount of data corresponding to a playback time and whose size is predefined for a period of time immediately preceding the trigger event.

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore K
• Righetti Niccolo′
• Mcneil Jr Jeffrey S
• Goda Akira
• Marquart Todd A
• Helm Mark A
• Golov Gil
• Binfet Jeremy
• Miccoli Carmine
• Puzzilli Giuseppina

Classifications

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F1/263

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• G06F3/0613

  in relation to throughput · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title