Adjustment of code rate as function of memory endurance state metric

Patent metadata

Field	Value
Publication number	US-11983067-B2
Application number	US-202217897869-A
Country	US
Kind code	B2
Filing date	Aug 29, 2022
Priority date	Aug 29, 2022
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

First claim

What is claimed is:

1. A method comprising:
determining, by a processing device, a value of a memory endurance state metric associated with a memory device in a memory sub-system;
determining a target value of a code rate based on the value of the memory endurance state metric; and
adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

2. The method of claim 1 , wherein the memory endurance state metric reflects a count of program erase cycles.

3. The method of claim 1 , wherein the memory endurance state metric reflects total bytes written and/or a raw bit error rate.

4. The method of claim 1 , wherein determining the target value of the code rate is performed using a data structure comprising a plurality of records, wherein each record of the plurality of records maps a specific value of a code rate to a corresponding value of the memory endurance state metric.

5. The method of claim 1 , wherein determining the target value of the code rate comprises:
determining the target value of the code rate according to sample data associated with a specified management unit of the memory device, wherein the sample data provides a plurality of records, and wherein each record of the plurality of records maps a specific value of a code rate corresponding to a value of the memory endurance state metric.

6. The method of claim 5 , wherein the specified management unit comprises a sacrificial block, wherein the sacrificial block is programed or erased at a rate faster than blocks designated for user data to provide the plurality of records.

7. The method of claim 1 , wherein adjusting the code rate comprises:
increasing a number of memory units used to store the host-originated data and decreasing a number of blocks used to store the error correction metadata in order to increase the code rate.

8. The method of claim 1 , wherein adjusting the code rate comprises:
decreasing a number of memory units used to store the host-originated data and increasing a number of blocks used to store the error correction metadata in order to decrease the code rate.

9. The method of claim 1 , wherein adjusting the code rate comprises:
increasing a number of memory units used to store the error correction metadata while keeping a number of blocks used to store the host-originated data unchanged in order to decrease the code rate.

10. The method of claim 1 , wherein adjusting the code rate further comprises:
decreasing a number of memory units used to store the error correction metadata while keeping a number of blocks used to store the host-originated data unchanged in order to increase the code rate.

11. The method of claim 1 , wherein adjusting the code rate further comprises:
responsive to determining that the value of the memory endurance state metric exceeds an end-of-life threshold, decreasing the code rate below a predefined threshold code rate.

12. The method of claim 1 , wherein adjusting the code rate further comprises:
responsive to determining that the value of the memory endurance state metric does not exceed a beginning-of-life threshold, increasing the code rate above a predefined threshold code rate.

13. The method of claim 1 , wherein adjusting the code rate further comprises:
responsive to determining that the value of the memory endurance state metric falls in a range, using a predefined code rate as the code rate.

14. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining a value of a memory endurance state metric associated with a segment of the memory device;
determining a target value of a code rate based on the value of the memory endurance state metric; and
adjusting the code rate associated with the segment of the memory device,

wherein the code rate reflects a ratio of an amount of bits designated for host data to a total amount of bits designated for the host data and error correction data.

15. The system of claim 14 , wherein the memory endurance state metric reflects a count of program erase cycles.

16. The system of claim 14 , wherein determining the target value of the code rate comprises:
determining the target value of the code rate according to a data structure comprising a plurality of records, wherein each record of the plurality of records maps a specific value of a code rate to a corresponding value of the memory endurance state metric.

17. The system of claim 14 , wherein determining the target value of the code rate comprises:
determining the target value of the code rate according to sample data associated with a specified management unit of the memory device, wherein the sample data provides a plurality of records, and wherein each record of the plurality of records maps a specific value of a code rate corresponding to a value of the memory endurance state metric.

18. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations, comprising:
monitoring a memory endurance state metric associated with a segment of a memory device in a memory sub-system;
determining whether the memory endurance state metric satisfies a criterion for adjusting a code rate; and
responsive to determining that the memory endurance state metric satisfies the criterion, adjusting the code rate associated with the segment of the memory device based on the memory endurance state metric, wherein the code rate reflects a ratio of an amount of bits designated for host data to a total amount of bits designated for the host data and error correction data.

19. The non-transitory computer-readable storage medium of claim 18 , wherein adjusting the code rate further comprises:
determining a value of the code rate according to a data structure comprising a plurality of records, wherein each record of the plurality of records maps a specific value of a code rate to a corresponding value of the memory endurance state metric.

20. The non-transitory computer-readable storage medium of claim 18 , wherein adjusting the code rate further comprises:
determining a value of the code rate according to sample data associated with a specified management unit of the memory device, wherein the sample data provides a plurality of records, and wherein each record of the plurality of records maps a specific value of a code rate corresponding to a value of the memory endurance state metric.

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Righetti Niccolo′
• Parthasarathy Sivagnanam
• Kaynak Mustafa N
• Helm Mark A
• Fitzpatrick James
• Russo Ugo

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/1435

  using file system or storage system metadata · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title