Threshold voltage distribution adjustment for buffer

Patent metadata

Field	Value
Publication number	US-11663104-B2
Application number	US-202217691957-A
Country	US
Kind code	B2
Filing date	Mar 10, 2022
Priority date	Aug 17, 2020
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory device; and
a processing device communicatively coupled to the memory device, wherein the processing device is to:
write, within a first set of threshold voltage distributions, received data to the memory device; and perform, in response to a determination that a trigger event has occurred, a touch up operation on the memory device that adjusts the first set of threshold voltage distributions to a second set of threshold voltage distributions having a larger read window between adjacent threshold voltage distributions than that of the first set of threshold voltage distributions.

2. The apparatus of claim 1 , wherein the processing device is to perform the touch up operation to adjust a read window between adjacent threshold voltage distributions corresponding to the data, while maintaining data states of the data.

3. The apparatus of claim 1 , wherein memory cells of the memory device are programmable to a first data state or a second data state and the processing device is to perform the touch up operation on only those memory cells of the memory device in the first data state.

4. The apparatus of claim 3 , wherein the processing device is to adjust a threshold voltage of those memory cells in the first data state to a higher threshold voltage.

5. The apparatus of claim 1 , wherein a read window is a distance between adjacent edges of respective voltage distributions of the first set of threshold voltage distributions or the second set of threshold voltage distributions.

6. The apparatus of claim 1 , wherein:
the first set of threshold voltage distributions is tailored to endurance of the memory device; and
the second set of threshold voltage distributions is tailored to reliability of the memory device.

7. The apparatus of claim 1 , wherein:
a location of the memory device configured for the data corresponds to a block of NAND memory cells; and
the processing device is to perform a touch up operation on each page of the block of NAND memory cells.

8. An apparatus, comprising:
a memory device; and a processing device communicatively coupled to the memory device, the processing device to:
write cyclic buffer data to the memory device within a first set of threshold voltage distributions; and convert, in response to a trigger event, the cyclic buffer data to snapshot data by performing a touch up operation on the cyclic buffer data to adjust the first set of threshold voltage distributions to a second set of threshold voltage distributions having a larger read window between adjacent threshold voltage distributions than that of the first set of threshold voltage distributions.

9. The apparatus of claim 8 , wherein the processing device is to operate, prior to the trigger event, a location of the memory device configured for the cyclic buffer data as a first-in-first-out (FIFO) buffer.

10. The apparatus of claim 8 , wherein the touch operation performed on the cyclic buffer data adjusts a read window between respective threshold voltage distributions associated with the cyclic buffer data without the cyclic buffer data being erased.

11. The apparatus of claim 10 , wherein the memory device comprises NAND flash memory cells.

12. The apparatus of claim 8 , wherein the cyclic buffer data corresponds to an amount of time-based telemetric sensor data predefined for a period of time immediately preceding the trigger event.

13. The apparatus of claim 8 , further comprising a primary power supply and a backup power supply coupled to the memory device, and wherein the processing device is configured to convert the cyclic buffer data to the snapshot data, while being powered by the primary power supply.

14. The apparatus of claim 13 , wherein the processing device is configured to convert the cyclic buffer data to the snapshot data, while being powered by the backup power supply in response to a loss of the primary power supply.

15. The apparatus of claim 8 , further comprising trigger circuitry to signal the processing device in response to the trigger event.

16. The apparatus of claim 8 , wherein the memory device is an event recorder storage device for an autonomous vehicle.

17. A method, comprising:
operating a location of a memory device configured for cyclic buffer data with a first set of threshold voltage distributions; and
converting, in response to a trigger event, the cyclic buffer data to snapshot data by operating the location of the memory device with a second set of threshold voltage distributions.

18. The method of claim 17 , further comprising converting the cyclic buffer data to the snapshot data without disturbing data states of the cyclic buffer data.

19. The method of claim 17 , further comprising converting the cyclic buffer data to the snapshot data without physically erasing the cyclic buffer data.

20. The method of claim 17 , further comprising flagging, subsequent to converting to the snapshot data, the location as storing the snapshot data.

Assignees

• Micron Technology Inc

Inventors

• Mcneil Jr Jeffrey S
• Righetti Niccolo′
• Muchherla Kishore K
• Goda Akira
• Marquart Todd A
• Helm Mark A
• Golov Gil
• Binfet Jeremy
• Miccoli Carmine
• Puzzilli Giuseppina

Classifications

• G06F11/3037

  where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00) · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C5/141

  Battery and back-up supplies · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title