Threshold voltage based on program/erase cycles

Patent metadata

Field	Value
Publication number	US-11776629-B2
Application number	US-202016995517-A
Country	US
Kind code	B2
Filing date	Aug 17, 2020
Priority date	Aug 17, 2020
Publication date	Oct 3, 2023
Grant date	Oct 3, 2023

Abstract

A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage.

First claim

What is claimed is:

1. A method, comprising:
in response to a memory device operating in a first portion of a service life of the memory device, programming at least one memory cell of the memory device to a first particular threshold voltage corresponding to a desired data state, wherein the first portion of the service life is defined by a program erase cycles (PEC) count from zero to a threshold PEC count; and
in response to the memory device operating in a second portion of the service life, programming at least one memory cell of the memory device to a second particular threshold voltage corresponding to the desired data state, wherein the second portion of the service life is defined by a PEC count greater than the threshold PEC count,
wherein the threshold PEC count, the first particular threshold voltage, the second particular threshold voltage, the first portion of service life, and the second portion of service life are determined prior to initiation of the service life and without reading a threshold voltage of the memory device,
wherein the second portion of the service life is subsequent to the first portion of the service life, and
wherein the second particular threshold voltage is different than the first particular threshold voltage.

2. The method of claim 1 , wherein the desired data state is a programmed state, and
wherein the second particular threshold voltage is greater than the first particular threshold voltage.

3. The method of claim 2 , further comprising:
during the first portion of the service life of the memory device, programming the at least one memory cell to a third particular threshold voltage corresponding to an erased state; and
during the second portion of the service life of the memory device, programming the at least one memory cell to a fourth particular threshold voltage corresponding to the erased state,
wherein the fourth particular threshold voltage is less than or more negative than the third particular threshold voltage.

4. The method of claim 1 , wherein the desired data state is an erased state, and
wherein the second particular threshold voltage is less than or more negative than the first particular threshold voltage.

5. The method of claim 1 , further comprising, during a third portion of the service life of the memory device subsequent to the second portion of the service life of the memory device, programming the at least one memory cell of the memory device to a third particular threshold voltage corresponding to the desired data state,
wherein the third particular threshold voltage is greater than the second particular threshold voltage.

6. The method of claim 1 , wherein at least one memory cell of the memory device is to store more than one bit, and
wherein the method further comprises:
during the first portion of the service life of the memory device, programming the at least one memory cell to a third particular threshold voltage corresponding to a different desired data state; and
during the second portion of the service life of the memory device, programming the at least one memory cell to a fourth particular threshold voltage corresponding to the different data state,
wherein the fourth particular threshold voltage is greater than the third particular threshold voltage, and
wherein the third particular threshold voltage is greater than the second particular threshold voltage.

7. A system, comprising:
a processing device; and
a memory device communicatively coupled to the processing device,
wherein the processing device is to:
responsive to the memory device operating in a first portion of a service life of the memory device, programming at least one memory cell of the memory device to a first particular threshold voltage corresponding to a desired data state, wherein the first portion of the service life is defined by a program erase cycles (PEC) count from zero to a threshold PEC count;
responsive to the memory device operating in a second portion of the service life, programming at least one memory cell of the memory device to a second particular threshold voltage corresponding to the desired state, wherein the second portion of service life is defined by a PEC count greater than the threshold PEC count,
wherein the threshold PEC count, the first particular threshold voltage, the second particular threshold voltage, the first portion of the service life, and the second portion of service life are determined prior to initiation of the service life and without reading a threshold voltage of the memory device, and
wherein the second portion of the service life is subsequent to the first portion of the service life.

8. The system of claim 7 , wherein the processing device is to:
responsive to the memory device operating in the first portion of the service life, program at least one memory cell of the memory device to a third particular threshold voltage corresponding to an erased state; and
responsive to the memory device operating in the second portion of service life, program at least one memory cell of the memory device to a fourth particular threshold voltage corresponding to the erased state, wherein the fourth particular threshold voltage is more negative than the third particular threshold voltage.

9. The system of claim 7 , wherein the desired state is a programmed state.

10. The system of claim 7 , wherein the system comprises a solid state drive to provide event recorder storage for an autonomous vehicle.

11. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
responsive to a memory device operating in a first portion of a service life, program at least one memory cell of the memory device to a first particular threshold voltage corresponding to a desired data state with a relatively small read window,
wherein the first portion of the service life is defined by a program erase cycles (PEC) count from zero to a threshold PEC count; and
responsive to the memory device operating in a first portion of a service life, program at least one memory cell of the memory device to a second particular threshold voltage corresponding to the desired data state with a relatively large read window,
wherein the second portion of service life is defined by a PEC count greater than the threshold PEC count, and
wherein the threshold PEC count, the first particular threshold voltage, the second particular threshold voltage, the first portion of the service life, and the second portion of service life are determined prior to initiation of the service life and without reading a threshold voltage of the memory device.

12. The medium of claim 11 , wherein the desired data state corresponds to a programmed state, and
wherein the relatively small read window is such that a magnitude of the first particular threshold voltage is relatively close to a magnitude of a third particular threshold voltage corresponding to an erased state.

13. The medium of claim 12 , further comprising instructions to program at least one memory cell of the memory device to the second particular threshold voltage with the relatively small read window within the first portion of the service life of the memory device to reduce degradation of the at least one memory cell,
wherein the first portion of the service life is early in the service life.

14. The medium of claim 11 , further comprising instructions to enlarge a read window in the second portion of service life of the memory device to improve data retention of at least one memory cell of the memory device near an end of the se

Assignees

• Micron Technology Inc

Inventors

• Righetti Niccolo'
• Muchherla Kishore K
• Mcneil Jr Jeffrey S
• Goda Akira
• Marquart Todd A
• Helm Mark A
• Golov Gil
• Binfet Jeremy
• Miccoli Carmine
• Puzzilli Giuseppina

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3495 Primary

  Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title