Acceleration of data queries in memory

Patent metadata

Field	Value
Publication number	US-11635906-B2
Application number	US-202016984429-A
Country	US
Kind code	B2
Filing date	Aug 4, 2020
Priority date	Aug 4, 2020
Publication date	Apr 25, 2023
Grant date	Apr 25, 2023

Abstract

The present disclosure includes apparatuses and methods for acceleration of data queries in memory. An example apparatus includes an array of memory cells and processing circuitry. The processing circuitry is configured to receive, from a host, a query for particular data in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that corresponds more closely to the search key than other data stored in the portions of the array of memory cells, and transfer the data that corresponds more closely to the search key than the other data to the host.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of memory cells; and
processing circuitry configured to:
receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, and wherein the host sets a maximum mismatch bit count and a minimum mismatch bit count for the query;
search portions of the array of memory cells for the particular data corresponding to the search key;
determine data stored in the portions of the array of memory cells that includes more bits that match corresponding bits in the search key than other data stored in the portions of the array of memory cells; and
transfer the data that includes more bits that match the corresponding bits in the search key than other data to the host, wherein the data that includes more bits that match the corresponding bits in the search key than the other data is not transferred to the host when an amount of bits in that data that do not match a corresponding bit in the search key is greater than the maximum mismatch bit count or less than the minimum mismatch bit count.

2. The apparatus of claim 1 , wherein the processing circuitry is configured to determine the data that includes more bits that match the corresponding bits in the search key based on an amount of current conducted by the portions of the array of memory cells.

3. The apparatus of claim 2 , wherein the amount of current conducted by a portion of the array of memory cells increases when more memory cells in that portion store data corresponding to bits in the search key.

4. The apparatus of claim 2 , wherein the amount of current conducted by a portion of the array of memory cells decreases when less memory cells in that portion store data corresponding to bits in the search key.

5. The apparatus of claim 2 , wherein the data stored in the portions of the array of memory cells that conduct more current are determined to include more bits that match the corresponding bits in the search key than the other data stored in the portions of the array of memory cells.

6. The apparatus of claim 2 , wherein the data stored in the portions of the array of memory cells that conduct less current are determined to include less bits that match the corresponding bits in the search key than the other data stored in the portions of the array of memory cells.

7. The apparatus of claim 1 , wherein the processing circuitry is configured to store the data that includes more bits that match the corresponding bits in the search key than the other data in a separate memory device.

8. The apparatus of claim 7 , wherein the separate memory device is a static random-access memory (SRAM) memory device.

9. The apparatus of claim 7 , wherein the query for the particular data stored in the array of memory cells includes a query for data corresponding to a number of data fields, including:
a logical block address (LBA) number;
an LBA offset; and
a count of bits that do not match corresponding bits in the search key.

10. The apparatus of claim 9 , wherein the number of portions of the array of memory cells whose data can be stored in the separate memory device corresponds to an amount of data included in each of the data fields.

11. The apparatus of claim 10 , wherein the amount of data included in each of the data fields is defined by the host.

12. An apparatus, comprising:
an array of memory cells; and
processing circuitry configured to:
receive, from a host, a query for data stored in the array of memory cells, wherein the the host sets a maximum mismatch bit count and a minimum mismatch bit count for the query;
search portions of the array of memory cells for the data;
determine data stored in the portions of the array of memory cells that includes more bits that match corresponding bits in a search key generated by the host than other data stored in the portions of the array of memory cells; and
transfer, to the host, only the data that includes more bits that match the corresponding bits in the search key than the other data, wherein the data that includes more bits that match the corresponding bits in the search key than the other data is not transferred to the host when an amount of bits in that data that do not match a corresponding bit in the search key is greater than the maximum mismatch bit count or less than the minimum mismatch bit count.

13. The apparatus of claim 12 , wherein the array of memory cells comprises a database.

14. The apparatus of claim 12 , wherein the array of memory cells is a three-dimensional (3D) NAND array of memory cells.

15. A system, comprising:
a host; and
a memory device coupled to the host, wherein:
the host is configured to:
set a maximum mismatch bit count for a query for particular data stored in the memory device and a minimum mismatch bit count for a query for the particular data stored in the memory device;
send, to the memory device, the query for the particular data stored in the memory device; and
generate a search key to denote the particular data; and

the memory device is configured to, in response to receiving the query:
search portions of the memory device for the particular data;
count a number of bits in each portion of the memory device that do not match the particular data denoted in the search key to determine data stored in the portions of the memory device that includes more bits that match corresponding bits in the query than other data stored in the portions of the memory device; and
transfer the data that includes more bits that match the corresponding bits in the search key than the other data to the host, wherein the data that includes more bits that match the corresponding bits in the search key is not transferred to the host when an amount of bits in that data that do not match a corresponding bit in the search key is greater than the maximum mismatch bit count for the query or less than the minimum mismatch bit count for the query.

16. The system of claim 15 , wherein the data stored in the portions of the memory device is encrypted.

17. The system of claim 16 , wherein the host is configured to decrypt the data stored in the host and the data stored in the memory device.

18. The system of claim 15 , wherein the query includes a command to search for the particular data in the memory device.

19. The system of claim 15 , wherein the particular data denoted in the search key is encrypted.

20. The system of claim 15 , wherein the memory device includes error correction circuitry configured to correct errors in the data that includes more bits that match corresponding bits in the search key than the other data.

21. The system of claim 20 , wherein the errors in the data that includes more bits that match corresponding bits in the search key than the other data are corrected before that data is sent to the host.

22. The system of claim 15 , wherein the host is configured to determine which portions of the array of memory cells include more bits that match corresponding bits in the search key than other portions of the array of memory cells by comparing the data sent to the host to a search key.

23. A method, comprising:
generating, by a host, a search key denoting particular data;
setting, by the host, a maximum mismatch bit count for a query for the particular data and a minimum mismatch bit count for the query for the particular data;
sending, to a memory device b

Assignees

• Micron Technology Inc

Inventors

• Helm Mark A
• Pawlowski Joseph T

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title