Status check using chip enable pin

Patent metadata

Field	Value
Publication number	US-12169461-B2
Application number	US-202217963773-A
Country	US
Kind code	B2
Filing date	Oct 11, 2022
Priority date	Dec 10, 2020
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.

First claim

What is claimed is:

1. A memory system, comprising:
one or more memory devices comprising one or more drivers;
a pin coupled with the one or more memory devices and configured to receive a chip enable signal for the one or more memory devices; and
one or more controllers coupled with the one or more memory devices and the pin, wherein the one or more controllers are configured to cause the memory system to:
bias the pin to a first voltage, the first voltage corresponding to a first status of the one or more memory devices, the first status indicating that the one or more memory devices are accessible;
bias the pin to a second voltage, the second voltage corresponding to a second status of the one or more memory devices, the second status indicating that the one or more memory devices are inaccessible; and
determine the first status, the second status, or both of the one or more memory devices based at least in part on comparing the first voltage and the second voltage to a set of voltages associated with statuses of the one or more memory devices.

2. The memory system of claim 1 , wherein the first voltage is lower than the second voltage.

3. The memory system of claim 1 , wherein, to bias the pin to the first voltage or to bias the pin to the second voltage, the one or more controllers are configured to cause the memory system to:
couple the pin with a voltage source based at least in part on the first status of the one or more memory devices, the second status of the one or more memory devices, or both.

4. The memory system of claim 1 , wherein the one or more controllers are configured to cause the memory system to bias the pin to the first voltage and the second voltage based at least in part on a resistance of the one or more drivers.

5. The memory system of claim 1 , wherein the one or more controllers are configured to cause the memory system to:
transmit the chip enable signal to the one or more memory devices;
determine the first status, the second status, or both of the one or more memory devices based at least in part on the chip enable signal; and
bias the pin to a third voltage based at least in part on the first status, the second status, or both of the one or more memory devices.

6. The memory system of claim 1 , wherein, to determine the first status, the second status, or both of the one or more memory devices, the one or more controllers are configured to cause the memory system to:
compare a current of the pin to a set of currents associated with the statuses of the one or more memory devices, wherein the current of the pin is based at least in part on the pin being biased to the first voltage or the second voltage.

7. The memory system of claim 1 , wherein the second voltage satisfies a threshold voltage that indicates that the one or more memory devices are inaccessible.

8. A method, comprising:
biasing, by one or more controllers, a pin configured to receive a chip enable signal for one or more memory devices to a first voltage, the first voltage corresponding to a first status of the one or more memory devices, the first status indicating that the one or more memory devices are accessible;
biasing, by the one or more controllers, the pin to a second voltage, the second voltage corresponding to a second status of the one or more memory devices, the second status indicating that the one or more memory devices are inaccessible; and
determining the first status, the second status, or both of the one or more memory devices based at least in part on comparing the first voltage and the second voltage to a set of voltages associated with statuses of the one or more memory devices.

9. The method of claim 8 , wherein the first voltage is lower than the second voltage.

10. The method of claim 8 , wherein biasing the pin to the first voltage or biasing the pin the second voltage comprises:
coupling the pin with a voltage source based at least in part on the first status of the one or more memory devices, the second status of the one or more memory devices, or both.

11. The method of claim 8 , wherein biasing the pin to the first voltage and the second voltage is based at least in part on a resistance of one or more drivers coupled with the one or more memory devices.

12. The method of claim 8 , further comprising:
transmitting the chip enable signal to the one or more memory devices;
determining the first status, the second status, or both of the one or more memory devices based at least in part on the chip enable signal; and
biasing the pin to a third voltage based at least in part on the first status, the second status, or both of the one or more memory devices.

13. The method of claim 8 , wherein determining the first status, the second status, or both of the one or more memory devices comprises:
comparing a current of the pin to a set of currents associated with the statuses of the one or more memory devices, wherein the current of the pin is based at least in part on the pin being biased to the first voltage or the second voltage.

14. The method of claim 8 , wherein the second voltage satisfies a threshold voltage that indicates that the one or more memory devices are inaccessible.

15. A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
bias, by one or more controllers, a pin configured to receive a chip enable signal for one or more memory devices to a first voltage, the first voltage corresponding to a first status of the one or more memory devices, the first status indicating that the one or more memory devices are accessible;
bias, by the one or more controllers, the pin to a second voltage, the second voltage corresponding to a second status of the one or more memory devices, the second status indicating that the one or more memory devices are inaccessible; and
determine the first status, the second status, or both of the one or more memory devices based at least in part on comparing the first voltage and the second voltage to a set of voltages associated with statuses of the one or more memory devices.

16. The non-transitory computer-readable medium of claim 15 , wherein the first voltage is lower than the second voltage.

17. The non-transitory computer-readable medium of claim 15 , wherein, to bias the pin to the first voltage or to bias the pin to the second voltage, the instructions are further executable by the one or more processors to:
couple the pin with a voltage source based at least in part on the first status of the one or more memory devices, the second status of the one or more memory devices, or both.

18. The non-transitory computer-readable medium of claim 15 , wherein the instructions are further executable by the one or more processors to bias the pin to the first voltage and the second voltage based at least in part on a resistance of one or more drivers coupled with the one or more memory devices.

19. The non-transitory computer-readable medium of claim 15 , wherein the instructions are further executable by the one or more processors to:
transmit the chip enable signal to the one or more memory devices;
determine the first status, the second status, or both of the one or more memory devices based at least in part on the chip enable signal; and
bias the pin to a third voltage based at least in part on the first status, the second status, or both of the one or more memory devices.

20. The non-transitory computer-readable medium of claim 15 , wherein to determine the

Assignees

• Micron Technology Inc

Inventors

• Kim Chulbum
• Helm Mark A
• Weinberg Yoav

Classifications

• G06F1/266

  Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title