Acceleration of data queries in memory

Patent metadata

Field	Value
Publication number	US-12367935-B2
Application number	US-202318514707-A
Country	US
Kind code	B2
Filing date	Nov 20, 2023
Priority date	Aug 4, 2020
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

First claim

What is claimed is:

1. An apparatus, comprising:
an array of memory cells; and
circuitry formed below the array of memory cells, wherein:
the circuitry formed below the array of memory cells includes a sense amplifier latch configured to sense data stored in the array of memory cells; and
the circuitry formed below the array of memory cells is further configured to:
receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host;
determine the sensed data stored in the array of memory cells that matches the search key; and
transfer the sensed data that matches the search key to the host.

2. The apparatus of claim 1 , wherein the circuitry formed below the array of memory cells comprises CMOS under array circuitry.

3. The apparatus of claim 1 , wherein the array of memory cells is a three-dimensional array of memory cells having a stair step structure.

4. The apparatus of claim 1 , wherein the circuitry formed below the array of memory cells includes a page buffer.

5. The apparatus of claim 1 , wherein the circuitry formed below the array of memory cells includes periphery support circuitry.

6. The apparatus of claim 1 , wherein the circuitry formed below the array of memory cells is configured to determine the sensed data stored in the array of memory cells that matches the search key by comparing the sensed data to the search key.

7. A method, comprising:
receiving, by circuitry formed below an array of memory cells of a memory device, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by a host;
determining, by the circuitry formed below the array of memory cells, data stored in a portion of the array that matches the search key based on an amount of current conducted by the portion of the array; and
transferring, by the circuitry formed below the array of memory cells, the data that matches the search key to the host.

8. The method of claim 7 , wherein the circuitry formed below the array of memory cells comprises logic circuitry.

9. The method of claim 7 , wherein the method includes determining the data stored in the portion of the array that matches the search key by:
sensing data stored in the portion of the array; and
comparing the sensed data to the search key.

10. The method of claim 9 , wherein the method includes determining the data stored in the portion of the array that matches the search key without transferring the sensed data to the host.

11. The method of claim 7 , wherein:
determining the data stored in the portion of the array that matches the search key comprises determining the data stored in the portion of the array that exactly matches the search key; and
transferring the data that matches the search key to the host comprises transferring the data that exactly matches the search key to the host.

12. An apparatus, comprising:
a three-dimensional array of memory cells; and
CMOS under array circuitry formed below the array of memory cells, wherein:
the CMOS under array circuitry formed below the array of memory cells includes a sense amplifier latch configured to sense data stored in portions of the array of memory cells; and
the CMOS under array circuitry formed below the array of memory cells is further configured to:
receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host;
determine the sensed data stored in the portions of the array of memory cells that matches the search key; and
transfer the sensed data that matches the search key to the host.

13. The apparatus of claim 12 , wherein the CMOS under array circuitry includes a plurality of page buffers.

14. The apparatus of claim 13 , wherein:
the three-dimensional array of memory cells comprises a plurality of planes of memory cells; and
each respective one of the plurality of page buffers corresponds to a different one of the plurality of planes of memory cells.

15. The apparatus of claim 13 , wherein the plurality of page buffers comprise four page buffers.

16. The apparatus of claim 13 , wherein the CMOS under array circuitry includes a plurality of row drivers that are contiguous to the plurality of page buffers.

17. The apparatus of claim 13 , wherein the plurality of page buffers are configured to sense the particular data stored in the array of memory cells.

18. The apparatus of claim 12 , wherein the three-dimensional array of memory cells and the CMOS under array circuitry are formed on a same chip of the apparatus.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Helm Mark A
• Pawlowski Joseph T

Classifications

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C15/046

  using non-volatile storage elements · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title