Multi-layer code rate architecture for copyback between partitions with different code rates

Patent metadata

Field	Value
Publication number	US-11829245-B2
Application number	US-202217696245-A
Country	US
Kind code	B2
Filing date	Mar 16, 2022
Priority date	Mar 16, 2022
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

First claim

What is claimed is:

1. A system comprising:
non-volatile memory comprising a first partition and a second partition, wherein the first partition is configured to store data in memory cells each storing a single bit of data, and the second partition is configured to store data in memory cells each storing two or more bits of data; and
a controller configured to:
generate first error correction code (ECC) data for user data, wherein the first ECC data provides a first capability for correcting at least one error in the user data;
store the user data and the first ECC data in the first partition;
generate second ECC data for the user data, wherein a combination of the first ECC data and the second ECC data provides a second capability for correcting at least one error in the user data, and the second capability is able to correct a greater number of errors than the first capability;
store the second ECC data outside of the first partition; and
copy the user data to the second partition using a copyback operation or using error correction, wherein:
copying the user data using the copyback operation comprises causing copying of the user data and the first ECC data to the second partition without error correction; and
copying the user data using error correction comprises performing error correction for the user data using the combination of the first and second ECC data.

2. The system of claim 1 , wherein the second ECC data is generated using the first ECC data.

3. The system of claim 1 , wherein the combination of the first and second ECC data is a concatenation of the first and second ECC data.

4. The system of claim 1 , wherein generating the first ECC data comprises generating a first parity check matrix.

5. The system of claim 4 , wherein generating the second ECC data comprises generating a second parity check matrix using the first parity check matrix.

6. The system of claim 1 , wherein the second ECC data is stored in memory cells each configured to store a single bit of data.

7. The system of claim 1 , wherein the second ECC data is stored in the non-volatile memory outside of the first and second partitions.

8. The system of claim 1 , wherein the first ECC data corresponds to a first code rate, the second ECC data corresponds to a second code rate, and the second code rate is smaller than the first code rate.

9. The system of claim 1 , wherein copying the user data to the second partition is performed without copying the second ECC data.

10. The system of claim 1 , wherein the copyback operation further comprises reading the user data from the first partition and writing the user data to the second partition without communicating any of the user data to the controller.

11. The system of claim 1 , wherein the copyback operation is a NAND flash internal copyback operation.

12. A system comprising:
non-volatile memory comprising a first partition and a second partition, wherein data stored in the first partition is stored in memory cells each configured to store charge representative of a single bit of data, and data stored in the second partition is stored in memory cells each configured to store charge representative of two or more bits of data; and
a controller configured to:
generate first error correction code (ECC) data for user data, wherein the first ECC data provides a first capability for correcting at least one error in the user data;
store the user data and the first ECC data in the first partition;
generate second ECC data for the user data, wherein a combination of the first ECC data and the second ECC data provides a second capability for correcting at least one error in the user data, and the second capability is able to correct a greater number of errors than the first capability;
store the second ECC data outside of the first partition;
determine a context associated with the stored user data; and
copy the user data to the second partition using a copyback operation or using error correction, wherein:
use of the copyback operation or the error correction is selected based on the determined context;
copying the user data using the copyback operation comprises causing copying of the user data and the first ECC data to the second partition without error correction; and
copying the user data using error correction comprises copying the user data to the second partition with error correction using at least one of the first ECC data or the second ECC data.

13. The system of claim 12 , wherein copying the user data using error correction is performed using the combination of first and second ECC data in response to determining that using the first ECC data without the second ECC data is insufficient to correct at least one error in the user data.

14. The system of claim 12 , wherein generating the second ECC data comprises generating the second ECC data as a function of the first ECC data.

15. The system of claim 12 , wherein copying the user data to the second partition using error correction further comprises:
attempting error correction using the first ECC data without the second ECC data; and
in response to determining a failure of the attempted error correction, performing error correction using the first and second ECC data.

16. The system of claim 12 , wherein copying the user data to the second partition using error correction further comprises:
correcting at least one error in the user data to provide corrected user data;
generating, by an encoder, third ECC data for the corrected user data; and
copying the corrected user data and the third ECC data to the second partition.

17. The system of claim 16 , wherein the third ECC data provides the first capability for correcting at least one error in the user data.

18. The system of claim 12 , wherein
based on the determined context, the user data is copied using error correction to provide corrected user data; and
the corrected user data is copied to the second partition.

19. The system of claim 18 , wherein determining the context comprises determining that the user data has been stored in the first partition for a time period that exceeds a threshold.

20. The system of claim 18 , wherein determining the context comprises determining that an error rate associated with the stored user data is greater than a threshold.

21. The system of claim 18 , wherein determining the context comprises evaluating at least one temperature associated with the stored user data.

22. The system of claim 21 , wherein evaluating the temperature associated with the stored user data comprises determining at least one of a temperature when the user data was stored in the first partition, or a temperature when copying the user data to the second partition.

23. The system of claim 18 , wherein determining the context comprises determining a number of program-erase cycles associated with the first partition.

24. The system of claim 12 , wherein the controller is further configured to:
receive a write command from a host device;
wherein the user data is stored in the first partition in response to receiving the write command.

25. The system of claim 12 , wherein the first ECC data comprises first parity bits for a low-density parity check (LDPC) code.

26. The system of claim 25 , wherein the second ECC data comprises second parity bits for the LDPC code.

27. The system of claim 12 , wherein the

Assignees

• Micron Technology Inc

Inventors

• Kaynak Mustafa N
• Muchherla Kishore Kumar
• Parthasarathy Sivagnanam
• Fitzpatrick James
• Helm Mark A

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• H03M13/293

  with erasure setting · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title