Microprocessor validation using random prepackaged generated test functions and user level scheduler
US-2026017160-A1 · Jan 15, 2026 · US
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Dusanapudi Manoj patents
Dusanapudi Manoj is listed as an inventor on 95 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Dusanapudi Manoj |
| Total patents | 95 |
| First publication | Apr 2, 2015 |
| Latest publication | Jan 15, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Hazard generating for speculative cores in a microprocessor
US-12450411-B2 · Oct 21, 2025 · US
Deterministic test program generation for evaluating cache coherency
US-2025149103-A1 · May 8, 2025 · US
Performance and reliability of processor store operation data transfers
US-12141071-B2 · Nov 12, 2024 · US
Validation of store coherence relative to page translation invalidation
US-12130749-B2 · Oct 29, 2024 · US
Cache coherence validation using delayed fulfillment of L2 requests
US-12118355-B2 · Oct 15, 2024 · US
Performance and reliability of processor store operation data transfers
US-2024028518-A1 · Jan 25, 2024 · US
Hazard generating for speculative cores in a microprocessor
US-2023195981-A1 · Jun 22, 2023 · US
Validation of store coherence relative to page translation invalidation
US-2023195649-A1 · Jun 22, 2023 · US
Cache coherence validation using delayed fulfillment of l2 requests
US-2023122466-A1 · Apr 20, 2023 · US
Recent patents
Latest publications not already listed above.
Validation of store coherence relative to page translation invalidation
US-2023105945-A1 · Apr 6, 2023 · US
Validation of store coherence relative to page translation invalidation
US-11620235-B1 · Apr 4, 2023 · US
Test case generation for a hardware state space
US-11163661-B2 · Nov 2, 2021 · US
List insertion in test segments with non-naturally aligned data boundaries
US-11094391-B2 · Aug 17, 2021 · US
Method, system, and apparatus for stress testing memory translation tables
US-11061821-B2 · Jul 13, 2021 · US
Test case generation for a hardware state space
US-2021042202-A1 · Feb 11, 2021 · US
Controlling segment layout in a stress test for a processor memory with a link stack
US-10877864-B2 · Dec 29, 2020 · US
Core pairing in multicore systems
US-10831620-B2 · Nov 10, 2020 · US
System and method for testing processor errors
US-10748637-B2 · Aug 18, 2020 · US
Efficiently generating effective address translations for memory management test cases
US-10713179-B2 · Jul 14, 2020 · US
Controlling segment layout in a stress test for a processor memory with a link stack
US-2020201728-A1 · Jun 25, 2020 · US
Method, system, and apparatus for stress testing memory translation tables
US-2020089621-A1 · Mar 19, 2020 · US
System and Method for Testing Processor Errors
US-2020035319-A1 · Jan 30, 2020 · US
Stress testing a processor memory with a link stack
US-10540249-B2 · Jan 21, 2020 · US
Method, system, and apparatus for stress testing memory translation tables
US-10521355-B2 · Dec 31, 2019 · US
Efficient testing of direct memory address translation
US-10489261-B2 · Nov 26, 2019 · US
Replicating test case data into a cache with non-naturally aligned data boundaries
US-10489259-B2 · Nov 26, 2019 · US
Efficient testing of direct memory address translation
US-10481991-B2 · Nov 19, 2019 · US
List insertion in test segments with non-naturally aligned data boundaries
US-10438682-B2 · Oct 8, 2019 · US
List insertion in test segments with non-naturally aligned data boundaries
US-2019287639-A1 · Sep 19, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 91 |
| Globalfoundries Inc | 3 |
| Int Business Machnes Corporation | 1 |
| Dusanapudi Manoj | 1 |
| Jayaraman Prasanna | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F11/263 | 46 |
| G06F11/2236 | 22 |
| G06F11/2635 | 19 |
| G06F12/1027 | 19 |
| G11C29/36 | 15 |