Hazard generating for speculative cores in a microprocessor

Patent metadata

Field	Value
Publication number	US-12450411-B2
Application number	US-202117554821-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Dec 17, 2021
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A system, mechanism, tool, programming product, processor, and/or method for generating a hazard in a processor includes: identifying one or more cache lines to invalidate in a second level memory of a processing core in the processor; invalidating, in response to identifying one or more cache lines to invalidate in the second level cache, the one or more identified cache lines in the second level memory; and invalidating, in response to invalidating the one or more identified cache lines in the second level memory, the corresponding one or more cache lines in a first level memory. In an aspect the hazard generating mechanism is triggered, preferably on demand, and includes in an approach searching for cache lines in the second level memory that are also in the first level memory.

First claim

What is claimed is:

1. A method for generating a hazard in a processor, the method comprising:
identifying one or more cache lines to invalidate in a second level memory of a processing core in the processor;
invalidating, in response to identifying the one or more cache lines to invalidate in the second level memory, the one or more identified cache lines in the second level memory; and
invalidating, in response to invalidating the one or more identified cache lines in the second level memory, the corresponding one or more cache lines in a first level memory.

2. The method of claim 1 , wherein:
the first level memory is a first level data cache in a processor core that is local to the processor core and the second level memory is a second level data cache in the processor, wherein the first level data cache is smaller and faster than the second level data cache.

3. The method of claim 2 , wherein the second level data cache is local to the processor core.

4. The method of claim 1 , wherein the processor is a multi-core processor and the method is performed in one of the processor cores of the multi-core processor.

5. The method of claim 1 , further comprising triggering a hazard generating mechanism, wherein in response to triggering the hazard generating mechanism the hazard generating system identifies the one or more cache lines in the second level memory to invalidate.

6. The method of claim 5 , further comprising triggering the hazard generating mechanism on demand.

7. The method of claim 5 , further comprising triggering the hazard generating mechanism via firmware.

8. The method of claim 1 , wherein identifying the one or more cache lines to invalidate in the second level memory comprises searching the second level memory.

9. The method of claim 8 , wherein searching the second level memory comprises a walk through the second level memory comparing cache lines in the second level memory with invalidating criteria.

10. The method of claim 8 , further comprising searching the second level memory according to an invalidating algorithm.

11. The method of claim 10 , wherein the invalidating algorithm comprises identifying only even cache lines in the second level memory that have their inclusivity bit set, wherein setting the inclusivity bit in the second level memory indicates that the cache line is located in the first level memory.

12. The method of claim 1 , wherein identifying the one or more cache lines in the second level memory to invalidate comprises reading an inclusivity bit in second level memory, wherein the inclusivity bit in the second level memory indicates the level of memory that owns a cache line.

13. The method of claim 1 , further comprising the second level memory communicating with the first level memory to invalidate the corresponding one or more cache lines in the first level memory.

14. Programming instructions embedded on a non-transitory media, the programming instructions executable on a processor, wherein the programming instructions, in response to being executed on the processor, are configured to:
identify one or more cache lines to invalidate in a second level memory of a processing core in the processor;
invalidate, in response to identifying the one or more cache lines to invalidate in the second level memory-cache, the one or more identified cache lines in the second level memory; and
invalidate, in response to invalidating the one or more identified cache lines in the second level memory, the corresponding one or more cache lines in a first level memory.

15. The programming instructions of claim 14 , wherein the programming instructions, in response to being executed on the processor, are configured to trigger a hazard generating mechanism, wherein in response to triggering the hazard generating mechanism the hazard generating system identifies the one or more cache lines in the second level memory to invalidate.

16. The programming instructions of claim 15 , wherein the programming instructions, in response to being executed on the processor, are configured to have the second level memory communicate with the first level memory the corresponding one or more cache lines in the first level memory to invalidate.

17. The programming instructions of claim 14 , wherein the programming instructions to identify the one or more cache line to invalidate in the second level memory, in response to being executed on the processor, are configured to search the second level memory.

18. The programming instructions of claim 17 , wherein the programming instructions to search the second level memory, in response to being executed on a processor, are configured to walk through the second level memory comparing cache lines in the second level memory with invalidating criteria.

19. The programming instructions of claim 17 , wherein the programming instructions to search the second level memory, in response to being executed on a processor, are configured to search the second level memory according to an invalidating algorithm.

20. The programming instructions of claim 14 , wherein the programming instructions to identify the one or more cache lines in the second level memory to invalidate, in response to being executed on a processor, are configured to read an inclusivity bit in second level memory, wherein the inclusivity bit in the second level memory indicates ownership of a cache line.

Assignees

• IBM

Inventors

• Kapoor Shakti
• Wu Nelson
• Dusanapudi Manoj

Classifications

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3818

  Decoding for concurrent execution · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F9/30058

  Conditional branch instructions · CPC title

• G06F2115/10

  Processors · CPC title